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88e3015/88E3018 datasheet integrated 10/100 fast ethernet transceiver doc. no. mv-s103657-00, rev. c october 26, 2006
no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including phot ocopying and recording, for any purpose, without the express written permission of marvell. marvell retain s the right to make changes to this document at any time, with out notice. marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the impli ed warranties of merchantability or fitness for any particular purpose. further, marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situati on if any such products failed. do not use marvell products in these types of equipment or applications. with respect to the products described herein, the user or recipient, in the absence of appropriate u.s. government authorizati on, agrees: 1) not to re-export or release any such information consisting of technology, software or source code controlled for national s ecurity reasons by the u.s. export control regulations ("ear"), to a national of ear country groups d:1 or e:2; 2) not to export the direct product of such technology or such software, to ear country groups d:1 or e:2, if such technology o r software and direct products thereof are controlled for national security reasons by the ear; and, 3) in the case of technology controlled for national security reasons under the ear where the direct product of the technology is a complete plant or component of a plant, not to export to ear country groups d:1 or e:2 the direct product of the plant or major component thereof, if such direct produ ct is controlled for national security reasons by the ear, or is subject to controls under the u.s. munitions list ("usml"). at all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this doc ument in connection with their receipt of any such information. copyright ? 2006. marvell international ltd. all rights reserved. marvell, the marvell logo, moving forward faster, alaska, fas twriter, datacom systems on silicon, libertas, link street, netgx, phyadvantage, prestera, raising the technology bar, the technology within, virtual cable tester, and yukon are registered trademarks of marvell. ants, anyvoltage, discovery, dsp switcher, feroceon, galnet, galt is, horizon, marvell makes it all possible, radlan, unimac, an d vct are trademarks of marvell. all other trademarks are the property of their respective owners. document status advance information this document contains design specifications fo r initial product developm ent. specifications may change without notice. contact marvell field application engineers for more information. preliminary information this document contains preliminary data, and a revision of this document will be published at a later date. specifications may change without notice. contact marv ell field application engineers for more information. final information this document contains specifications on a product that is in final release. specifications may change without notice. contact marvell field application engineers for more information. revision code: rev. c advance technical publication: 1.30 doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 2 document classification: propri etary information october 26, 2006, advance
88e3015/88E3018 integrated 10/100 fast ethernet transceiver copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 3 o verview the marvell ? 88e3015/88E3018 devices are the fourth generation marvell ? dsp-based physical layer trans- ceivers for fast ethernet applications. the devices con- tain all the active circuitry to convert data streams to and from a media access controller (mac) and the physical media. the 88e3015/88E3018 devices incor- porate ieee 802.3u auto-negotiation in support of both 100base-tx and 10base-t networks over twisted- pair cable in full-duplex or half-duplex mode. the 88e3015/88E3018 devices both support the reduced gigabit media inde pendent interface (rgmii), and the media indepen dent interface (mii). the 88e3015/88E3018 devices feature a mode of oper- ation supporting ieee comp liant 100base-fx fiber- optic networks. additionally, the 88e3015/88E3018 devices implement far-end fault indication (fefi) in order to provide a mechanism for transferring informa- tion from the local station to the link partner that indi- cates a remote fault has occurred in 100base-fx mode. the 88e3015/88E3018 devices feature the marvell vir- tual cable tester ? (vct?) technology, which enables it managers and networking equipment manufacturers to remotely analyze the quality and characteristics of the attached cable plant. the 88e3015/88E3018 devices use advanced mixed- signal processing and power management techniques for extremely low power dissipation and high port count system integration. the 88 e3015/88E3018 devices are manufactured in an all cmos process. 88e3015/88E3018 s pecific f eatures the 88E3018 device, housed in a 64-pin qfn package, offers a pin-upgradeable path toward future gigabit ethernet phy designs. the 88E3018 device includes support for ieee 1149.1 jtag standard test access port and boundary scan. the 88e3108 device is avail- able in industrial grade (rohs 6/6 compliant package only) the 88e3015 device, housed in a 56-pin qfn package, provides a cost-efficient, increased board savings option to the 88E3018. f eatures ? ieee 802.3 compliant 100base-tx and 10base- t ports ? reduced gigabit media independent interface (rgmii) ? media independent interface (mii) support ? source synchronous mii support ? virtual cable tester ? (vct?) technology ? pecl interface supporting 100base-fx applica- tions ? automatic mdi/mdix crossover for 10base-t and 100base-tx ? jumbo frame support to 10 kbytes with up to 150 ppm clock frequency difference ? ieee 802.3u auto-negotiation support for auto- matic speed and duplex selection ? far-end fault indication (fefi) support for 100base-fx applications ? supports 802.3ah unidirectional enable ? energy detect feature ? baseline wander correction ? auto-calibration for mac interface outputs ? coma mode support ? flexible serial management interface (mdc/mdio) for register access ? programmable interrupt to minimize polling ? ieee 1149.1 standard test access port and boundary scan compatible (88E3018 only) ? supports three (3) leds per port ? 0.15 m standard digital cmos process ? 56-pin qfn 8 mm x 8 mm package (88e3015 device) ? 64-pin qfn 9 mm x 9 mm package (88E3018 device) ? available in industrial grade (88E3018 device, rohs 6/6 package only)
88e3015/88E3018 integrated 10/100 fast ethernet transceiver doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 4 document classification: proprietary information october 26, 2006, advance 88e3015 device functional block diagram 88E3018 device functional block diagram table 1: 88e3015/88E3018 devices feature differences 88e3015 88E3018 package 56-pin qfn 64-pin qfn mii yes yes rgmii yes yes virtual cable tester ? yes yes fiber support yes yes parallel leds yes yes power management yes yes jtag support no yes industrial grade no rohs 6/6 package only mdip/n[1] mdip/n[0] sigdet xtal_in auto mdix crossover dac adc digital adaptive equalizer baseline wander canceller 10 mbps receiver 10/100 receive pcs 10/100 transmit pcs fx link & auto negotiation rgmii or mii rxd[3:0] rx_ctrl tx_ctrl txd[3:0] clock/ reset management interface mdc mdio xtal_out led/ configuration led[2:0] tx_clk rx_clk config[3:0] crs col vref rx_er resetn coman 2.5v regulator 1.2v regulator ctrl25 dis_reg12 mdip/n[1] mdip/n[0] sigdet auto mdix crossover dac adc digital adaptive equalizer baseline wander canceller 10 mbps receiver 10/100 mbps receive pcs 10/100 mbps transmit pcs fx link & auto negotiation rgmii or mii management interface mdc mdio led/ configuration led[2:0] config[3:0] jtag boundary scan xtal_in clock/ reset xtal_out resetn coman 2.5v regulator 1.2v regulator ctrl25 dis_reg12 rxd[3:0] rx_ctrl tx_ctrl txd[3:0] tx_clk rx_clk crs col vref rx_er
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 5 table of contents s ection 1. s ignal d escription .............. .............. .............. .............. ........... 9 1.1 88e3015 device 56-pin qfn pinout ............. ................ ............. ............. ............. ......... 9 1.2 88E3018 device 64-pin qfn pinout ............. ................ ............. ............. ............. ....... 10 1.3 pin description ............................................................................................................ 1 1 1.3.1 pin type definitions ...................................................................................................... .... 11 1.3.2 88e3015 56-pin qfn assignments - alphabetical by signal name................................. 21 1.3.3 88E3018 64-pin qfn assignments - alphabetical by signal name................................. 22 s ection 2. f unctional d escription ............... ................ ............... ........... 23 2.1 mac interface............................................................................................................... 24 2.1.1 reduced gigabit media independent interface (r gmii)............. .............. .............. .......... 24 2.1.2 media independent interface (mi i)............ .............. .............. .............. ............ ........... ....... 25 2.1.3 source synchronous mii................................................................................................... 2 6 2.2 serial management interface ...................................................................................... 27 2.2.1 mdc/mdio read and write operations............ .............. .............. .............. .............. ....... 27 2.2.2 preamble suppression.................................... .................................................................. 28 2.2.3 programming interrupts .................................................................................................... 28 2.3 transmit and receive functi ons ............................................................................... 29 2.3.1 transmit side network interface..................... .................................................................. 29 2.3.2 encoder................................................................................................................... .......... 29 2.3.3 receive side network interfac e........................................................................................ 29 2.3.4 decoder ................................................................................................................... ......... 30 2.3.5 auto-negotiation ...... .............. .............. .............. .............. ........... ........... ........... ........... ..... 31 2.4 power management ..................................................................................................... 32 2.4.1 ieee power down mode . .............. .............. .............. .............. ........... ............ ........... ....... 32 2.4.2 energy detect +tm......................................................................................................... .. 32 2.4.3 normal 10/100 mbps operation........................................................................................ 32 2.4.4 coma mode ................................................................................................................. .... 33 2.5 regulators and power supplies................................................................................. 34 2.5.1 avdd ...................................................................................................................... .......... 34 2.5.2 avddc ..................................................................................................................... ........ 34 2.5.3 avddr ..................................................................................................................... ........ 34 2.5.4 avddx..................................................................................................................... ......... 35 2.5.5 dvdd...................................................................................................................... .......... 35 2.5.6 vddo...................................................................................................................... .......... 35 2.5.7 vddor ..................................................................................................................... ........ 35 2.6 hardware configuration.............................................................................................. 36
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 6 document classification: proprieta ry information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.7 far end fault indication (fefi) .............. .....................................................................38 2.8 802.3ah unidirectional enable .................. ..................................................................38 2.9 virtual cable tester? feat ure .....................................................................................39 2.10 auto mdi/mdix crossover......................... ..................................................................40 2.11 led interface .............................................................................................................. ..41 2.11.1 manual override.......................................................................................................... ..... 41 2.11.2 phy control .............................................................................................................. ....... 42 2.11.3 led polarity ............................................................................................................. ........ 46 2.11.4 stretching and blinking.................................................................................................. ... 46 2.12 automatic and manual impedance calibrat ion .........................................................47 2.12.1 mac interface calibration circuit ................ ..................................................................... 47 2.12.2 mac interface calibration re gister definitions ...... .......................................................... 47 2.12.3 changing auto calibration targets .................................................................................. 48 2.12.4 manual settings to the cali bration registers .................................................................. 48 2.13 crc error counter .......................................................................................................52 2.13.1 enabling the crc error counter. ............ .............. .............. .............. ........... ........... ........ 52 2.14 ieee 1149.1 controller ................................................................................................53 2.14.1 bypass instruction ....................................................................................................... ..... 53 2.14.2 sample/preload instruction .............................................................................................. 5 3 2.14.3 extest instruction....................................................................................................... ....... 55 2.14.4 the clamp instruction .................................................................................................... .. 55 2.14.5 the high-z instruction ................................................................................................... .55 2.14.6 id code instruction...................................................................................................... ... 55 s ection 3. r egister d escription ................ ................ ................. ............ 56 s ection 4. e lectrical s pecifications ................... .............. ............ ........ 87 4.1. absolute maximum ratings ........................................................................................87 4.2. recommended operating c onditions ......... ................. ............. ............ ............. ........88 4.3 package thermal informatio n .....................................................................................89 4.3.1 88e3015 device 56-pin qfn package ............ ................................................................ 89 4.3.2 88E3018 device 64-pin qfn package ............ ................................................................ 90 4.4 current consumption ..................................................................................................91 4.4.1 current consumption avdd + center tap ...................................................................... 91 4.4.2 current consumption avddc.......................................................................................... 91 4.4.3 current consumption dvdd ............................................................................................ 92 4.4.4 current consumption vddo + vddor........................................................................... 92 4.5. dc operating conditions ............................................................................................93 4.5.1 non-mac interface digital pins........................................................................................ 93 4.5.2 stub-series transceiver logic (sstl_2)......... ................................................................ 94
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 7 4.5.3 ieee dc transceiver parameters ............. .............. .............. ............ ........... ........... ......... 96 4.6 ac electrical specificati ons ........................................................................................97 4.6.1 reset and configuration timing ....................................................................................... 97 4.6.2 xtal_in input clock timing ............................................................................................ 98 4.7 mii interface timing......................................................................................................99 4.7.1 100 mbps mii transmit timing - non source synchronous ............................................. 99 4.7.2 10 mbps mii transmit timing - non source synchronous ............................................... 99 4.7.3 100 mbps mii transmit timi ng - source synchronous................................................... 100 4.7.4 10 mbps mii transmit timing - source synchronous..................................................... 100 4.7.5 100 mbps mii receive timing ........................................................................................ 101 4.7.6 10 mbps mii receive timing .......................................................................................... 101 4.8 rgmii interface timing ..............................................................................................102 4.8.1 rgmii transmit timing................................................................................................... 10 2 4.8.2 rgmii receive timing.................................................................................................... 10 3 4.9 latency timing ...........................................................................................................105 4.9.1 mii to 100base-tx transmit latency timing ......... .............. ............ ........... ........... ....... 105 4.9.2 mii to 10base-t transmit latency timing .................................................................... 105 4.9.3 100base-tx to mii receive latency timing .. ............................................................... 107 4.9.4 10base-t to mii receive late ncy timing ......... .............. .............. .............. ........... ....... 107 4.9.5 rgmii to 100base-tx transmit latency timing........................................................... 109 4.9.6 rgmii to 10base-t transmit la tency timing ...... .............. .............. ........... ........... ....... 109 4.9.7 100base-tx to rgmii receiv e latency timing....... .............. .............. .............. .......... 110 4.9.8 10base-t to rgmii receive la tency timing ........... .............. .............. .............. .......... 110 4.10 serial management timing ......................... ...............................................................111 4.11 jtag timing ...............................................................................................................1 12 s ection 5. p ackage m echanical d imensions ............... .............. ........... 113 5.1 88e3015 package mechanical dimensions..............................................................113 5.2 88E3018 package mechanical dimensions..............................................................115 s ection 6. a pplication e xamples ................. ................ .............. ........... 117 6.1 10base-t/100base-tx circuit application ............................................................117 6.2 fx interface to 3.3v fiber transceiver .....................................................................118 6.3 transmitter - receiver diagram ................. ...............................................................119 6.4 88E3018 to 88e3015 backpl ane connection - 100base-fx interface....... ............120 6.5 88E3018 to another vendor?s phy - 100base-fx interface through a backplane121 6.6 marvell? phy to marvell phy direct conn ection ....................................................122
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 8 document classification: proprieta ry information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver s ection 7. o rder i nformation ................. ................. ................ ............. 123 7.1 ordering part numbers and package mark ings ......................................................123
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 9 signal description 88e3015 device 56-pin qfn pinout section 1. signal description 1.1 88e3015 device 56-pin qfn pinout the 88e3015 is manufactured in a 56-pin qfn. figure 1: 88e3015 integrated 10base-t/100base-tx fast ethernet transceiver 56-pin qfn package config[1] config[2] config[3] dvdd led[0] vddo led[1] led[2] resetn dis_reg12 dvdd avddr ctrl25 sigdet rx_er crs col vddo nc mdin[1] mdip[1] avdd mdin[0] mdip[0] config[0] tx_ctrl txd[3] txd[2] tx_clk txd[1] txd[0] vref vddor rxd[3] rxd[2] rx_clk rxd[0] rx_ctrl nc coman mdc nc vddo mdio dvdd xtal_out xtal_in hsdacp 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 42 41 40 39 38 37 36 35 34 33 32 31 56 55 54 53 52 51 50 49 48 47 46 45 44 43 88e3015 13 avddr 14 avddx 27 tstpt 28 rset 30 hsdacn 29 avddc vddor rxd[1] epad - vss
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 10 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 1.2 88E3018 device 64-pin qfn pinout the 88E3018 is manufactured in a 64-pin qfn. figure 2: 88E3018 integrated 10base-t/100base-tx fast ethernet transceiver 64-pin qfn package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 nc avdd nc mdip[1] mdin[1] col nc nc crs rx_er sigdet ctrl25 vddo mdin[0] mdip[0] tstpt vddor rx_clk rxd[2] rxd[3] vddor txd[1] txd[2] txd[3] tx_ctrl config[0] vref rxd[1] rxd[0] rx_ctrl 17 18 19 20 21 22 23 24 25 26 30 31 32 27 28 29 64 63 62 61 60 59 58 57 56 55 51 50 49 54 53 52 config[1] config[2] config[3] coman led[0] vddo led[1] led[2] resetn avddr avddr avddx dvdd trstn dis_reg12 dvdd mdc nc vddo mdio tdi tck tms dvdd xtal_out hsdacn avddc rset tdo xtal_in nc hsdacp tx_clk txd[0] epad - vss top view 88E3018
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 11 signal description pin description 1.3 pin description 1.3.1 pin type definitions pin type definition h input with hysteresis i/o input and output i input only o output only pu internal pull up pd internal pull down d open drain output z tri-state output ma dc sink capability
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 12 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 2: rgmii interface 88e3015 88E3018 pin name type description 52 60 tx_clk/txc i rgmii transmit clock provides a 25 mhz or 2.5 mhz reference clock with 50 ppm tolerance depending on speed. in rgmii mode, tx_clk is used as txc. 55 63 tx_ctrl/tx_ctl i rgmii transmi t control. tx_en is presented on the rising edge of tx_clk. in rgmii mode, tx_ctrl is used as tx_ctl. a logical derivative of tx_en and tx_er is pre- sented on the falling edge of tx_clk. 54 53 51 50 62 61 59 58 txd[3]/td[3] txd[2]/td[2] txd[1]/td[1] txd[0]/td[0] i rgmii transmit data. in rgmii mode, txd[3:0] are used as td[3:0]. the transmit data nibble is presented on txd[3:0] on the rising edge of tx_clk. 45 53 rx_clk/rxc o rgmii receive clock provides a 25 mhz or 2.5 mhz reference clock with 50 ppm tolerance derived from the received data stream depending on speed. in rgmii mode, rx_clk is used as rxc. 41 49 rx_ctrl/ rx_ctl o rgmii receive control. rx_dv is presented on the rising edge of rx_clk. in rgmii mode, rx_ctrl is used as rx_ctl. a logical derivative of rx_dv and rx_er is pre- sented on the falling edge of rx_clk. 47 46 43 42 55 54 51 50 rxd[3]/rd[3] rxd[2]/rd[2] rxd[1]/rd[1] rxd[0]/rd[0] o rgmii receive data. in rgmii mode, rxd[3:0] are used as rd[3:0]. the receive data nibble is presented on rxd[3:0] on the rising edge of rx_clk.
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 13 signal description pin description table 3: mii interface 88e3015 88E3018 pin name type description 52 60 tx_clk i/o, z mii transmit cl ock. tx_clk provides a 25 mhz and 2.5 mhz clock reference for tx_ctrl, tx_er, and txd[3:0], depending on the speed. tx_clk is an output when in normal mii mode, and is an input in source synchronous mii mode. 54 53 51 50 62 61 59 58 txd[3] txd[2] txd[1] txd[0] i mii transmit data. txd[3:0] presents the data nib- ble to be transmitted onto the cable. txd[3:0] is synchronous to tx_clk. 55 63 tx_ctrl/tx_en mii transmit en able. in mii mode, tx_ctrl is used as tx_en. when tx_ctrl is asserted, data on txd[3:0] along with tx_er is encoded and transmitted onto the cable. tx_en is synchronous to tx_clk. 45 53 rx_clk o, z mii receive clock. rx_clk provides a 25 mhz and 2.5 mhz clock reference for rx_ctrl, rx_er, and rxd[3:0] depending on the speed. 47 46 43 42 55 54 51 50 rxd[3] rxd[2] rxd[1] rxd[0] o, z mii receive data. symbols received on the cable are decoded and presented on rxd[3:0]. rxd[3:0] is synchronous to rx_clk. 41 49 rx_ctrl/rx_dv mii receive data valid. data received on the cable is decoded and presented on rxd[3:0] and rx_er. in mii mode, rx_ctrl is used as rx_dv. rx_ctrl is synchronous to rx_clk. 17 19 rx_er i/o, z mii receive error. when rx_er and rx_ctrl are both asserted, the signals indicate an error symbol is detected on the cable. when rx_er is asserted with rx_ctrl de- asserted, a false carrier is detected on the cable. rx_er is synchronous to rx_clk.
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 14 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 18 20 crs o, z mii carrier sense. crs asserts when the receive medium is non-idle. crs is asynchronous to rx_clk, and tx_clk. 19 23 col o, z mii collision. in full-duplex modes, col is always low. in 10base-t/100b ase-tx half-duplex modes, col asserts only when both the transmit and receive media are non-idle. in 10base-t half-duplex mode, col is asserted to indicate signal quality error (sqe). disable sqe by clearing register 16.2 to zero. col is asynchronous to rx_clk, and tx_clk. table 3: mii interface (continued) 88e3015 88E3018 pin name type description
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 15 signal description pin description table 4: network interface 88e3015 88E3018 pin name type description 26 25 31 30 mdip[0] mdin[0] i/o media dependent interface[0]. in mdi configuration, mdi[0] is used for the trans- mit pair. in mdix configuration, mdi[0] is used for the receive pair. 23 22 26 25 mdip[1] mdin[1] i/o media dependent interface[1]. in mdi configuration, mdi[1] is used for the receive pair. in mdix configuration, mdi[1] is used for the transmit pair. 16 18 sigdet i in 100base-fx mode, sigdet indicates whether a signal is detected by the fiber optic transceiver. in 100base-tx/10base-t modes, this pin should not be left floating. it should be tied either high or low. table 5: serial management interface 88e3015 88E3018 pin name type description 38 48 mdc i mdc is the clock reference for the serial manage- ment interface. a continuous clock stream is not required (i.e., mdc can be stopped when the mdc/ mdio master is not sending a command). the maximum frequency supported is 8.33 mhz. 35 45 mdio i/o mdio is the management data. mdio is used to transfer management data in and out of the device synchronously to mdc. this pin requires a pull-up resistor in a range from 1.5 kohm to 10 kohm.
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 16 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 6: led 88e3015 88E3018 pin name type description 8 9 led[2]/interrupt o parallel led outputs. see section 2.11 "led inter- face" on page 41 for led interface details. see section 2.2.3 "programming interrupts" on page 28 for interrupt details. 7 8 led[1] o parallel led outputs. see section 2.11 "led inter- face" on page 41 for details. 5 6 led[0] o parallel led outputs. see section 2.11 "led inter- face" on page 41 for details. table 7: jtag 88e3015 88E3018 pin name type description -- 43 tdi i boundary scan test data input. tdi contains an internal 150 kohm pull-up resistor. -- 41 tms i boundary scan test mode select input. tms con- tains an internal 150 kohm pull-up resistor. -- 42 tck i boundary scan test clock input. tck contains an internal 150 kohm pull-up resistor. -- 11 trstn i boundary scan test reset input. active low. trstn contains an internal 150 kohm pull-up resistor as per the 1149.1 specification. after power up, the jtag state machine should be reset by applying a low signal on this pin, or by keeping tms high and applying 5 tck pulses, or by pulling this pin low by a 4.7 kohm resistor. -- 44 tdo o boundary scan test data output.
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 17 signal description pin description table 8: clock/configuration/reset 88e3015 88E3018 pin name type description 32 38 xtal_in i reference clock. 25 mhz 50 ppm tolerance crys- tal reference or oscillator input. 33 39 xtal_out o reference clock. 25 mhz 50 ppm tolerance crys- tal reference. when the xtal_out pin is not con- nected, it should be left floating. xtal_out is used for crystal only. this pin should be left floating when an oscillator input is connected to xtal_in. 3 2 1 56 3 2 1 64 config[3] config[2] config[1] config[0] i hardware configuration. see section 2.6 "hardware configuration" on page 36 for details. 9 10 resetn i hardware reset. active low. xtal_in/xtal_out must be active for a minimum of 10 clock cycles before the rising edge of resetn. resetn must be pulled high for normal operation. 49 57 vref i mac interface input voltage reference. must be set to vddor/2 when used as 2.5v sstl_2. set to vddor when used as 2.5v lv cmos. 39 4 coman i coma control. active low. if resetn is low then coman has no effect. coman contains an internal 150 kohm pull-up resistor. 0 = in power saving mode 1 = normal operation
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 18 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 9: regulator & reference 88e3015 88E3018 pin name type description 28 33 rset i constant voltage reference. external 2 kohm 1% resistor connection to vss is required for this pin. 10 12 dis_reg12 i 1.2v regulator disable. tie to vddo to disable, tie to vss to enable. 15 17 ctrl25 o 2.5v regulator control. this signal ties to the base of the bjt. if the 2.5v regulator is not used it can be left floating. table 10: test 88e3015 88E3018 pin name type description 31 36 hsdacp o test pin. these pins have 49.9 ohm internal termination. they should be brought out to a via or pad to facili- tate debug. if debug is not important and there are board space constraints, this pin can be left float- ing. 30 35 hsdacn o test pin. these pins have 49.9 ohm internal termination. they should be brought out to a via or pad to facili- tate debug. if debug is not important and there are board space constraints, this pin can be left float- ing. 27 32 tstpt o test point. leave unconnected.
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 19 signal description pin description table 11: power & ground 88e3015 88E3018 pin name type description 24 28 avdd power analog supply. 2.5v. avdd can be supplied exter- nally with 2.5v, or via the 2.5v regulator. 29 34 avddc power analog supply - 2.5v or 3.3v. avddc must be supplied externally. do not use the 2.5v regulator to power avddc. 12 13 14 15 avddr power 1.2v regulator supply - 2.5v avddr can be supplied externally with 2.5v, or via the 2.5v regulator. if the 1.2v regulator is not used, avddr must still be tied to 2.5v. 14 16 avddx power 2.5v regulator supply - 3.3v avddx must be supplied externally. note that this supply must be the same voltage as avddc. if the 2.5v regulator is not used, then it means a 2.5v supply is in the system. avddx should be left floating. 4 11 34 5 13 40 dvdd digital core supply - 1.2v. dvdd can be supplied externally with 1.2v, or via the 1.2v regulator. 6 20 36 7 24 46 vddo power 2.5v or 3.3v non-mac interface digital i/o supply. vddo must be supplied externally. do not use the 2.5v regulator to power vddo. 44 48 52 56 vddor power 2.5v or 3.3v mac interface digital i/o supply. vddor must be supplied externally. do not use the 2.5v regulator to power vddor. epad epad vss ground ground to digital core. the 64-pin qfn package has an exposed die pad (e-pad) at its base. this e-pad must be soldered to vss. refer to the package mechanical drawings for the exact location and dimensions of the epad. 21 37 40 21 22 27 29 37 47 nc nc no connect. these pins are not bonded to the die and can be tied to anything.
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 20 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 12: i/o state at various test or reset modes pin(s) isolate loopback software reset hardware reset power down power down and isolate mdip/ n[1:0] active active tri-state tri -state tri-state tri-state tx_clk tri-state active activ e tri-state active tri-state rxd[0] rxd[2] rxd[3] rxd[1] rx_dv rx_er crs col tri-state active low low low tri-state rx_clk tri-state active reg. 28.1 state 1 = active 0 = low low reg. 28.1 state 1 = active 0 = low tri-state mdio active active active tri-state active active led active active active high high high tdo tri-state tri-state tri-state tri-state tri-state tri-state
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 21 signal description pin description 1.3.2 88e3015 56-pin qfn assignme nts - alphabetical by signal name pin # pin name pin # pin name 24 avdd 37 nc 29 avddc 40 nc 12 avddr 9 resetn 13 avddr 28 rset 14 avddx 45 rx_clk 19 col 41 rx_ctrl 39 coman 17 rx_er 56 config[0] 42 rxd[0] 1 config[1] 43 rxd[1] 2 config[2] 46 rxd[2] 3 config[3] 47 rxd[3] 18 crs 16 sigdet 15 ctrl25 27 tstpt 10 dis_reg12 52 tx_clk 4 dvdd 55 tx_ctrl 11 dvdd 50 txd[0] 34 dvdd 51 txd[1] 30 hsdacn 53 txd[2] 31 hsdacp 54 txd[3] 5 led[0] 6 vddo 7led[1] 20vddo 8led[2] 36vddo 38 mdc 44 vddor 25 mdin[0] 48 vddor 22 mdin[1] 49 vref 35 mdio epad vss 26 mdip[0] 32 xtal_in 23 mdip[1] 33 xtal_out 21 nc
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 22 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 1.3.3 88E3018 64-pin qfn assign ments - alphabetical by signal name pin # pin name pin # pin name 28 avdd 47 nc 34 avddc 10 resetn 14 avddr 33 rset 15 avddr 53 rx_clk 16 avddx 49 rx_ctrl 23 col 19 rx_er 4 coman 50 rxd[0] 64 config[0] 51 rxd[1] 1 config[1] 54 rxd[2] 2 config[2] 55 rxd[3] 3 config[3] 18 sigdet 20 crs 42 tck 17 ctrl25 43 tdi 12 dis_reg12 44 tdo 5dvdd 41tms 13 dvdd 11 trstn 40 dvdd 32 tstpt 35 hsdacn 60 tx_clk 36 hsdacp 63 tx_ctrl 6 led[0] 58 txd[0] 8 led[1] 59 txd[1] 9 led[2] 61 txd[2] 48 mdc 62 txd[3] 30 mdin[0] 7 vddo 25 mdin[1] 24 vddo 45 mdio 46 vddo 31 mdip[0] 52 vddor 26 mdip[1] 56 vddor 21 nc 57 vref 22 nc epad vss 27 nc 38 xtal_in 29 nc 39 xtal_out 37 nc
functional description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 23 section 2. functional description figure 3 shows the functional block for each of the 88e 3015/88E3018 devices. the transmitter and transmit pcs block are fully described on page 29 . the receiver and receive pcs block are fully described on page 29 . figure 3: 88e3015 device functional block diagram figure 4: 88E3018 device functional block diagram mdip/n[1] mdip/n[0] sigdet xtal_in auto mdix crossover dac adc digital adaptive equalizer baseline wander canceller 10 mbps receiver 10/100 receive pcs 10/100 transmit pcs fx link & auto negotiation rgmii or mii rxd[3:0] rx_ctrl tx_ctrl txd[3:0] clock/ reset management interface mdc mdio xtal_out led/ configuration led[2:0] tx_clk rx_clk config[3:0] crs col vref rx_er resetn coman 2.5v regulator 1.2v regulator ctrl25 dis_reg12 mdip/n[1] mdip/n[0] sigdet auto mdix crossover dac adc digital adaptive equalizer baseline wander canceller 10 mbps receiver 10/100 mbps receive pcs 10/100 mbps transmit pcs fx link & auto negotiation rgmii or mii management interface mdc mdio led/ configuration led[2:0] config[3:0] jtag boundary scan xtal_in clock/ reset xtal_out resetn coman 2.5v regulator 1.2v regulator ctrl25 dis_reg12 rxd[3:0] rx_ctrl tx_ctrl txd[3:0] tx_clk rx_clk crs col vref rx_er
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 24 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.1 mac interface the mac interfaces that are availa ble for each device are listed in table 1, ?88e3015/88E3018 devices feature differences,? on page 4 . all ports on the devices operate in the same interface mode that is selected. 2.1.1 reduced gigabit media independent interface (rgmii) the 88e3015/88E3018 device supports the rgmii specification (version 1.2a, 9/22/2000, version 2.0, 04/2002 - instead of hstl, it supports 2.5v sstl_2.). figure 5: rgmii signal diagram the interface runs at 2.5 mhz for 10 mbps and 25 mhz for 100 mbps. the tx_clk signal is always generated by the mac, and the rx_clk signal is generated by the phy. during packet reception, rx_clk may be stretched on eith er the positive or negativ e pulse to accommodate the transition from the free running clock to a data synchr onous clock domain. when the speed of the phy changes, a similar stretching of the positive or negative pulse is allowed. no glitching of the clocks is allowed during speed transitions. the mac must hold tx_ctrl low until the mac has ensured that tx_ctrl is operating at the same speed as the phy. tx_clk txd[3:0] rxd[3:0] tx_ctrl rx_ctrl rx_clk mac phy txc td[3:0] rd[3:0] tx_ctl rx_ctl rxc rgmii interface
functional description mac interface copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 25 2.1.2 media independ ent interface (mii) the 88e3015/88E3018 device supports the media independent interface. figure 6: mii signal diagram when the mii mode is selected, both tx_clk and rx_clk source 2.5 mhz and 25 mhz for 10 mbps and 100 mbps respectively. rxd[3:0] crs rx_dv rx_er col rx_clk mac phy rxd[3:0] crs rx_ctrl rx_er col rx_clk mii interface tx_clk tx_clk txd[3:0] tx_en txd[3:0] tx_ctrl
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 26 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.1.3 source synchronous mii the 88e3015/88E3018 device supports source synchronous mii. figure 7: source synchronous mii signal diagram the source synchronous mii is identical to the mii, except the tx_clk is an input. refer to section 4.7 for timing details. rxd[3:0] crs rx_dv rx_er col rx_clk mac phy rxd[3:0] crs rx_ctrl rx_er col rx_clk mii interface tx_clk tx_clk txd[3:0] tx_en txd[3:0] tx_ctrl
functional description serial management interface copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 27 2.2 serial management interface the serial management interface provides access to the internal registers via the mdc and mdio pins and is compliant to ieee 802.3u section 22. mdc is the managem ent data clock input and can run from dc to a maxi- mum rate of 8.33 mhz. mdio is the management data input/output and is a bi-d irectional signal that runs synchro- nously to mdc. the mdio pin requires a 1.5 kohm pul l-up resistor that pulls the mdio high during idle and turnaround times. 2.2.1 mdc/mdio read and write operations all the relevant serial management regi sters are implemented as well as seve ral optional registers. a description of the registers can be found in section 3. "register description" on page 56 . figure 8: typical mdc/mdio read operation figure 9: typical mdc/ mdio write operation table 13 is an example of a read operation. table 13: serial management interface protocol 32-bit preamble start of frame opcode read = 10 write = 01 5-bit phy device address 5-bit phy register address 2-bit turn- around read = z0 write = 10 16-bit data field idle 11111111 01 10 01100 00000 z0 0001001100000000 11111111 mdc mdio (sta) 0 1 1 0 0 1 1 0 0 0 0 0 0 0 z 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 z z mdio (phy) z z z z idle start opcode (read) phy address register address ta register data idle example 1 0 mdc mdio (sta) 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 z z idle start opcode (write) phy address register address ta register data idle 0 z example z
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 28 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.2.2 preamble suppression the 88e3015/88E3018 devices are permanently programm ed for preamble suppression. a minimum of one idle bit is required between operations. 2.2.3 programming interrupts when register 22:11:8 is set to 1110, the interrupt func tionality is mapped to the led[ 2] pin.the interrupt function drives the led[2] pin active whenever an interrupt event is enabled by programming register 18. the polarity of the interrupt signal is determined by register 25.14. this function minimizes the need for polling via the serial management interface. table 14 shows t he interrupts that may be programmed. register 18 determines whether the led[2] pin is asserted when an interru pt event occurs. register 19 reports interrupt status. when an interrupt event occurs, the co rresponding bit in register 19 is set and remains set until register 19 is read via the serial management interface. wh en interrupt enable bits are not set in register 18, inter- rupt status bits in register 19 are still set when the co rresponding interrupt events occur. however, the led[2] pin is not asserted. the led[2] pin is active as long as at least one interrupt st atus bit is set in register 19 with its corresponding inter- rupt enable bit set in register 18, and register 22:11:8 = 1110. to de-assert the led[2] pin: ? clear of register 19 via a serial management read ? disable the interrupt enable by writing register 18 table 14: programmable interrupts register address programmable interrupts 18.14 speed changed interrupt enable 18.13 duplex changed interrupt enable 18.12 page received interrupt enable 18.11 auto-negotiation completed interrupt enable 18.10 link status changed interrupt enable 18.9 symbol error interrupt enable 18.8 false carrier interrupt enable 18.7 fifo over/underflow interrupt enable 18.6 mdi/mdix crossover changed enable 18.4 energy detect changed enable 18.1 polarity changed enable 18.0 jabber interrupt enable
functional description transmit and receive functions copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 29 2.3 transmit and receive functions the transmit and receive paths for the 88e3015/88e301 8 device are described in the following sections. 2.3.1 transmit side network interface 2.3.1.1 multi-mode tx digi tal to analog converter the 88e3015/88E3018 device incorporates a multi-mode tr ansmit dac to generate filtered mlt-3, nrzi, or manchester coded symbols. the transmit dac performs signal wave shaping to reduce em i. the transmit dac is designed for very low parasitic loading capacitances to im prove the return loss requirem ent, which allows the use of low cost transformers. 2.3.1.2 slew rate control and waveshaping in 100base-tx mode, slew rate control is used to mi nimize high frequency emi. in 10base-t mode, the output waveform is pre-equalized via a digital filter. 2.3.2 encoder 2.3.2.1 100base-tx in 100base-tx mode, the transmit data stream is 4b/5b encoded, serialized, and scram bled. upon initialization, the initial scrambling seed is determined by the phy address. the datastream is then mlt-3 coded. 2.3.2.2 10base-t in 10base-t mode, the transmit data is serialized and conver ted to manchester encoding. 2.3.2.3 100base-fx in 100base-fx mode , the transmit data stream is 4b/5b en coded, serialized, and converted to nrzi. 2.3.3 receive side network interface 2.3.3.1 analog to digital converter the 88e3015/88E3018 device incorporates an advanced high speed adc on each receive channel with greater resolution for better snr, and therefor e, lower error rates. patented architec tures and design techniques result in high differential and integral linearity, high power suppl y noise rejection, and low metastability error rate. 2.3.3.2 baseline wander canceller the 88e3015/88E3018 device employs an advanced baseli ne wander cancellation circuit to automatically com- pensate for this dc shift. it minimizes the effect of dc baseline shift on the overall error rate. 2.3.3.3 digital adaptive equalizer the digital adaptive equalizer removes inter-symbol interf erence at the receiver. the digital adaptive equalizer takes unequalized signals from adc output and uses a co mbination of feedforward equalizer (ffe) and decision feedback equalizer (dfe) for the best-o ptimized signal-to-noise (snr) ratio.
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 30 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.3.3.4 link monitor the link monitor is responsible for determining if link is established with a link partner. in 10base-t mode, link monitor function is performed by detecting the presenc e of valid link pulses (nlps) on the mdi pins. in 100base-tx mode, link is esta blished by scrambled idles. see section 2.8 for unidirectional enable. 2.3.3.5 copper signal detection in 100base-tx mode, the signal detection function is bas ed on the receive signal energy detected on the mdi pins that is continuously qualifi ed by the squelch detect circuit, and the local receiver acquiring lock. 2.3.3.6 fiber signal detection the sigdet pin is used to qualify whether there is rece ive energy on the line. register 16.6 determines the polar- ity of the sigdet pin. when register 16. 6 is set low, the sigdet pin polarity is active high, otherwise the polarity is active low. 2.3.4 decoder 2.3.4.1 100base-tx in 100base-tx mode, th e receive data stream is reco vered and converted to nrz. the nrz stream is descram- bled and aligned to the symbol boundaries. the aligned dat a is then parallelized and 5b/4b decoded. the receiver does not attempt to decode the data stream unless the scrambler is locked. the descrambler ?locks? to the scram- bler state after detecting a sufficient number of consecut ive idle code-groups. once locked, the descrambler con- tinuously monitors the data stream to make sure that it has not lost synchronization. the descrambler is always forced into the unlocked state when a link failure condition is detected, or when insufficient idle symbols are detected. 2.3.4.2 10base-t in 10base-t mode, the reco vered 10base-t signal is decoded from ma nchester to nrz, and then aligne d. the alignment is necessary to insure that the start of frame delimiter (sfd) is aligned to the nibble boundary. 2.3.4.3 100base-fx in 100base-fx mode the receive data st ream is received and converted to nrz. the decoding process is identi- cal to 100base-tx except no descrambling is necessary.
functional description transmit and receive functions copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 31 2.3.5 auto-negotiation the 88e3015/88E3018 device c an auto-negotiate to operate in 10base-t or 100base-tx if auto-negotiation is enabled, then the 88e3015/88E3018 de vices negotiate with the link partner to determine the speed and duplex with which to operat e. if the link partner is unable to auto-negotiate, the 88e3015/88E3018 devices go into the parallel detect mode to determine the s peed of the link partner. under parallel detect mode, the duplex mode is fixed at half-duplex. 2.3.5.1 register update auto-negotiation is initiated upon any of the following conditions: ? power up reset ? hardware reset ? software reset ? restart auto-negotiation ? transition from power down to power up ? changing from the link-up state to the linkfail state changes to the anegen, speedlsb, and duplex bits (r egisters 0.12, 0.13, and 0.8, respectively) do not take effect unless one of the following takes place: ? software reset (swreset bit - register 0.15) ? restart auto-negotiation (restartaneg bit - register 0.9) ? transition from power down to power up (pwrdwn bit - register 0.11) ? the link goes down the auto-negotiation advertisement regist er (register 4) is internally latched once every time auto-negotiation enters the ability detect state in the arbitration state machine. henc e, a write into the au to-negotiation advertis- ment register has no effect once t he 88e3015/88E3018 devices begin to transmit fast link pulses (flps). this guarantees that a sequence of flps trans mitted is consistent with one another. the next page transmit register (register 7) is inter nally latched once every time auto-negotiation enters the next page exchange state in the arbitration state machine. 2.3.5.2 next page support the 88e3015/88E3018 devices support the use of next page during auto-negotiation. by default, the received base page and next page are stored in t he link partner ability register - base page (register 5). the 88e3015/ 88E3018 devices have an option to write the received next page into the link partner next page register - regis- ter 8 - (similar to the description provided in the ieee 802.3ab standard) by programming the reg8nxtpg bit (phy specific control regist er - register 16.12).
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 32 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.4 power management the 88e3015/88E3018 devices support advanced power management modes that conserve power. three low power modes are supported in the 88e3015/88E3018 devices. ? ieee 802.3 22.2. 4.1.5 compliant power down ? energy detect+ tm ? coma mode ieee 22.2.4.1.5 power down co mpliance allows for the phy to be placed in a low-po wer consumption state by register control. energy detect+ tm allows the 88e3015/88E3018 devices to wake up when energy is detec ted on the wire with the additional capability to wake up a link partner. the 10base-t link pulses are sent once every second while listen- ing for energy on the line. coma mode shuts down the phy into a low power state. table 15 displays the low power operating mode selection. 2.4.1 ieee power down mode the standard ieee power down mode is entered by setting register 0.11 equal to o ne. in this mode, the phy does not respond to any mac interface signals except the mdc/mdio. it also does not respond to any activity on the cat 5 cable. in this power down mode, the phy cannot wake up on its own by detecting activity on the cat 5 cable. it can only wake up by clearing the pwrdwn bit to 0. 2.4.2 energy detect + tm when register 16.14 is enabled, the energy detect +? mode is enabled. in this mode, the phy sends out a sin- gle 10 mbps nlp (normal link pulse) every one second. if the 88e3015/88E3018 devices are in energy detect+ mode, it can wake a connected device. the 88e 3015/88E3018 devices also respond to mdc/mdio. 2.4.3 normal 10/100 mbps operation normal 10/100 mbps operation can be ent ered by either using a register write during the energy detect mode. table 15: operating mode selection power mode how to activate mode ieee power down pwrdwn bit write (register 0.11) energy detect+ tm register edet bit write (register 16.14) coma coman pin
functional description power management copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 33 2.4.4 coma mode coma mode shuts down the phy into a low power state when it is not being used. when the phy is in the coma mode, the phy is completely non-functional including register access. coma mode is entered when the coman pin is set low. if hardware reset pin (resetn) and the coma pin (com an) are asserted simultaneou sly the hardware reset function has priority over the coma function. if the phy is disabled by removing any one or more of the external power supplies then the coman pin has no functionality. if the phy is re-enabled then the proper power up sequence must be followed and a hardware reset applied before the phy enters into the normal operating state. if the reference clock (xtal_in, xtal_out) stops when the phy is disabled then the reference clock must be restarted and hardware reset must be applied before the phy enters into the normal operating state. if all external power supplies remain powered up and the reference clock continues to run then the phy can enter and exit the coma state without the need for hardware rese t by simply controlling the coman pin. if xtal_in is attached to an oscillator instead of a crystal and if the re ference clock can be cleanly s witched between toggling at 25 mhz and non-toggling state without g litches then the xtal_in can be stop ped if the relationship shown in figure 10 can be met. tstop should be at least 1 ms. tstart should be at least 0 ms. note that if the power supply and reference clock requiremen ts can be met then all registers will retain their values during the coma state. figure 10: xtal_in to coman relationship resetn coman xtal_in toggling not toggling toggling t stop t stop
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 34 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.5 regulators and power supplies the 88e3015/88E3018 device can operate from a single 2.5v or 3.3v supply if the regulators are used. if regula- tors are not used then a 2.5v and 1.2v supply are needed. ta b l e 1 6 lists the valid combinations of regulator usage. the vddo supply can run at 2.5v or 3.3v and that the vddor supply can ru n at 2.5v or 3.3v. the 2.5v gener- ated by the 2.5v regulator must not be used to supply vddo or vddor. the avddc and avddx must always be at the same voltage level if avddx is not floating. the 2.5v regulator is not used if ctrl25 is left floating and not connected to a bjt. the 1.2v regulator is disabled when dis_reg12 is tied to vddo. it is enabled when di s_reg12 is tied to vss. 2.5.1 avdd avdd is used as the 2.5v analog supply. avdd can be supplied externally with 2.5v, or via the 2.5v regulator. 2.5.2 avddc avddc is used as the high voltage analog supply and can run on 2.5v or 3.3v. avddc must be supplied externally. do not use the 2.5v regulator to power avddc. 2.5.3 avddr avddr is used as the 2.5v supply to the internal regulator that generates the 1.2v digital supply. avddr can be supplied externally with 2.5v, or via the 2.5v regulator. table 16: power supply options supply configuration option pin name avddc avddx avdd avddr dvdd comment high voltage analog 2.5v regulator 2.5v analog 1.2v regulator 1.2v digital single 3.3v supply need external bjt dis_reg12 = vss 3.3v external 3.3v external 2.5v from bjt 2.5v from bjt 1.2v from internal regulator 3.3v supply and 1.2v supply need external bjt dis_reg12 = vddo 3.3v external 3.3v external 2.5v from bjt 2.5v from bjt 1.2v external single 2.5v supply do not connect exter- nal bjt dis_reg12 = vss 2.5v external floating 2.5v external 2.5v external 1.2v from internal regulator 2.5v supply and 1.2v supply do not connect exter- nal bjt dis_reg12 = vddo 2.5v external floating 2.5v external 2.5v external 1.2v external
functional description regulators and power supplies copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 35 if the 1.2v regulator is not used , avddr must still be tied to 2.5v. 2.5.4 avddx avddx is used as the 3.3v supply to the exte rnal regulator that generates the 2.5v supply. avddx must be supplied externally. note that this supply must be the same voltage as avddc. if the 2.5v regulator is not used, then the ctrl25 pin should be left floa ting. in this particular case when the 2.5v regulator is not used, the avddx pin should be left floating. 2.5.5 dvdd dvdd is used as the 1.2v digital supply. dvdd can be supplied externally with 1.2v, or via the 1.2v regulator. all dvdd pins should be shorted together. a decoupling capa citor should be attached to pin 11 of the 88e3015 device and pin 13 of the 88E3018 device. 2.5.6 vddo vddo supplies the non-mac interface digital i/o pins. the voltage range is 2.5v or 3.3v. vddo must be supplied externally. do not use the 2.5v regulator to power vddo. note the crs, col, and rx_er pins are on the vddo supply. 2.5.7 vddor vddor supplies the mac interface digital i/o pins. the voltage should be 2.5v or 3.3v. vddor must be supplied externally. do not use the 2.5v regulator to power vddor. three options are supported: ? 2.5v lvcmos ? 3.3v lvcmos ? 2.5v sstl_2 the vref pin should be set to 0.5 x vddor for sstl_2 behavior. the vref pin should be tied to vddor for lvcmos behavior. note that 3.3v sstl_2 is not supported. note the crs, col, and rx_er pins are not on the vddor supply.
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 36 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.6 hardware configuration the 88e3015/88E3018 devices are configured by tying led[2:0], crs, col, vddo , or vss to config[3:0]. after the deassertion of reset the 88e3015/88E3018 will be hardware configured. note led[2], crs, and col should not be tied to config[2:0 ]. use vddo to set bits [1:0] of config[2:0] to ?11?. the config pins should not be left floating. the led, crs, and col outputs a bit stream during initia lization that is used by the config pin inputs. the bit values are latched at the deassertion of hardwar e reset. the bit stream mapping is shown in table 17 table 17: three bit mapping pin bits 2,1,0 vss 000 led[0] 001 led[1] 010 led[2] 011 crs 100 col 110 vddo 111
functional description hardware configuration copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 37 the 3 bits for each config pin are mapped as shown in ta b l e 1 8 . each bit in the configuration is defined as shown in ta b l e 1 9 table 18: configuration mapping pin bit 2 bit 1 bit 0 config[0] reserved phyad[1] phyad[0] config[1] reserved phyad[3] phyad[2] config[2] reserved ena_xc phyad[4] config[3] mode[2] mode[1] mode[0] table 19: configuration definition bits definition bits affected phyad[4:0] phy address none ena_xc 0 = default disable auto-crossover 16.5:4 in 100base-fx mode, this should be disabled. 1 = default enable auto-crossover mode[2:0] 000 = copper - rgmii, receive clock transition when data transi- tions 28.11:10, 28.3 001 = copper - rgmii, receive clock transition when data stable 010 = fiber - rgmii, receive clock transition when data transitions 011 = copper - mii 100 = fiber - mii 110 = copper - source synchronous mii 111 = fiber - rgmii, receive clock transition when data stable
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 38 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 20 clarifies how the mode[2:0] affects the register defaults. 2.7 far end fault indication (fefi) far end fault indication provides a mechanism for transferri ng information from the local station to the link partner that a remote fault has occurred in 100base-fx mode. a remote fault is an error in the link that one station can de tect while the other one cannot. an example of this is a disconnected wire at a station?s transmitter. this station is receiving valid data and detects that the link is good via the link monitor, but is not able to detect that it s transmission is not propa gating to the other station. a 100base-fx station that detect s this remote fault modifies its transmitted idle stream pattern from all ones to a group of 84 ones followed by one zero. this is referred to as the fefi idle pattern. the fefi function is controlled by the fefi bits in 100base-fx mode. register 16.8 enables and disables the fefi functi on. this bit has no effect in 10base-t and 100base-tx modes. 2.8 802.3ah unidirectional enable the 88e3015/88E3018 devices support the 802.3ah unidirecti onal enable function. when this function is enabled the phy transmit path is enabled even if there is no link established. to enable unidirectional transmitting, all the following conditions must be met: ? unidirectional is enabled (0.5 = 1) ? auto-negotiation is disabled (0.12 = 0) ? full- duplex enabled (0.8 = 1). register 1.7 indicates that the phy is able to transmit from the media inde pendent interface regardless of whether the phy has determined that a valid link has been established. table 20: mode[2:0] to re gister default mapping mode[2:0] mac interface mode fiber/copper 28.11:10 28.3 000 (config3 = vss) 00 0 001 (config3 = led[0]) 01 0 010 (config3 = led[1]) 00 1 011 (config3 = led[2]) 10 0 100 (config3 = crs) 10 1 110 (config3 = col) 11 0 111 (config3 = vddo) 01 1
functional description virtual cable tester? feature copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 39 2.9 virtual cable tester ? feature the 88e3015/88E3018 devices virtual cable tester (vct?) feature uses time domain reflectometry (tdr) to determine the quality of the cables, connectors, and terminations. some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismat ch, bad connectors, termination mismatch, and bad magnetics. the 88e3015/88E3018 devices transmit a signal of know n amplitude (+1v) down each of the two pairs of an attached cable. it will conduct the cable diagnostic test on each pair, testing the tx and rx pairs sequentially. the transmitted signal will continue down the cable until it refl ects off of a cable imperfect ion. the magnitude of the reflection and the time it takes for the reflection to co me back are shown in the vct registers 26.12:8, 26.7:0, 27.12:8, and 27.7:0 respectively. using the information from the vct registers 26 and 27, the distance to the problem location and the type of problem can be determined. for example, the time it take s for the reflection to come back, can be converted to distance using the cable fault distance trend line tables in figure 11 . the polarity and magnitude of the reflection together with the distance will indicate t he type of discontinuity. for example, a +1v reflection will indicate an open close to the phy and a -1v reflection will indicate a short close to the phy. when the cable diagnostic feature is activated by setting register 26.15 bit to one, a pre-determined amount of time elapses before a test pulse is trans mitted. this is to ensure that the link partner loses link, so that it stops sending 100base-tx idles or 10 mbit data packets. this is necessary to be able to perform the tdr test. the tdr test can be performed either when there is no link part ner or when the link partner is auto-negotiating or sending 10 mbit idle link pulses. if the 88e3015/88E3018 devices receive a continuous signal for 125 ms, it will declare test failure because it cannot start the tdr test. in the test fail case, the received data is not valid. the results of the test are also summariz ed in register 26. 14:13 and 27.14:13. ? 11 = test fail (the tdr test could not be run for reasons explained above) ? 00 = valid test, normal cable (no short or open in cable) ? 10 = valid test, open in cable (impedance > 333 ohms) ? 01 = valid test, short in cable (impedance < 33 ohms) the definition for shorts and opens is arbitrary and the us er can define it anyway they desire using the information in the vct registers. the impedance mismatch at the loca tion of the discontinuity could also be calculated know- ing the magnitude of the reflection. refe r to the app note "virtual cable tester ? -- how to use tdr results" for details. figure 11: cable fault distance trend line tx/rx y = 0.7861x - 18.862 0 100 200 0 50 100 150 200 250 300 re g26[7:0], re g27[7:0] length
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 40 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.10 auto mdi/mdix crossover the 88e3015/88E3018 devices automatically determine whet her or not it needs to cross over between pairs so that an external crossover cable is not required. if th e 88e3015/88E3018 devices interoperate with a device that cannot automatically correct for crossover, the 88e3015/88 e3018 devices make the necessary adjustment prior to commencing auto-negotiation. if the 88e3015/88E3018 dev ices interoperate with a device that implements mdi/ mdix crossover, a random algorithm as described in ieee 802.3 section 40.4.4 determines which device per- forms the crossover. when the 88e3015/88E3018 devices in teroperate with legacy 10base-t devices that do not implement auto- negotiation, the 88e3015/88E3018 devices follow the same algorithm as described above since link pulses are present. however, when interoperating with legacy 100base- tx devices that do not implement auto-negotiation (i.e. link pulses are not present), th e 88e3015/88E3018 devices use signal dete ct to determine whether or not to crossover. the auto mdi/mdix crossover function can be disabled via register 16.5:4. the 88e3015/88E3018 devices are set to mdi mode by default if auto mdi/mdix crossover is disabled at hard- ware reset. auto mdi/mdix should be disabl ed for 100base-fx mode. mdi sh ould be forced for 100base-fx. the pin mapping in mdi and mdix modes is specified in table 21 . refer to figure 33 on page 117 for magnetics details. table 21: mdi/mdix pin functions physical pin mdix mdi 100base-tx 10base-t 100base-tx 10base-t mdip/n[1] transmit transmit receive receive mdip/n[0] receive receive transmit transmit
functional description led interface copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 41 2.11 led interface the leds can either be controlled by the phy or contro lled externally, independent of the state of the phy. 2.11.1 manual override external control is achieved by writing to the phy manual led override register 25.5:0. any of the leds can be turned on, off, or made to blink at variable rates ind ependent of the state of the phy. this independence elimi- nates the need for driving leds from the mac or the cpu. if the leds are driven from the cpu located at the back of the board, the led lines crossing the entire board will pick up noise. this noise will cause emi issues. also, pcb layout will be more difficult due to the additional lines routed across the board. when the leds are controlled by the phy, the activity of the leds is determined by the state of the phy. each led can be programmed to indicate various phy states, with variable blink rate. any one of the leds can be controlled independently of the other leds (i.e one led can be externally controlled while another led can be contro lled by the state of the phy). table 22: manual override bits field description 25.5:4 forceled2 00 = normal 01 = blink[1] 10 = led off 11 = led on 25.3:2 forceled1 00 = normal 01 = blink 10 = led off 11 = led on 25.1:0 forceled0 00 = normal 01 = blink 10 = led off 11 = led on
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 42 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.11.2 phy control manual override is disabled (25.5:4, 25.3:2, 25.1:0 is set to 00) then the led behavio r is defined by register 22.11:8, 22.7:4, and 22.3:0 ( table 23 ). if speed is selected then the led behav ior is further qual ified by register 24.8:6, 24.5:3 , and 24.2:0 ( ta b l e 2 4 ). see 2.2.3 "programming interrupts" when 22.11:8 is set to 1110. table 23: phy led control bits field description 22.11:8 led2 led2 control. this is a global setting. 0000 = colx 0001 = error 0010 = duplex 0011 = duplex/colx 0100 = speed 0101 = link 0110 = tx 0111 = rx 1000 = act 1001 = link/rx 1010 = link/act 1011 = act (blink mode) 1100 = tx (blink mode) 1101 = rx (blink mode) 1110 = interrupt 1111 = force off
functional description led interface copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 43 22.7:4 led1 led1 control. this is a global setting. 0000 = colx 0001 = error 0010 = duplex 0011 = duplex/colx 0100 = speed 0101 = link 0110 = tx 0111 = rx 1000 = act 1001 = link/rx 1010 = link/act 1011 = act (blink mode) 1100 = tx (blink mode) 1101 = rx (blink mode) 1110 = colx (blink mode) 1111 = force off table 23: phy led control (continued) bits field description
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 44 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 22.3:0 led0 led0 control. this is a global setting. 0000 = colx 0001 = error 0010 = duplex 0011 = duplex/colx 0100 = speed 0101 = link 0110 = tx 0111 = rx 1010 = link/act 1011 = act (blink mode) 1100 = tx (blink mode) 1101 = rx (blink mode) 1110 = colx (blink mode) 1111 = force off table 23: phy led control (continued) bits field description
functional description led interface copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 45 table 24: speed dependent behavior bits field description 24.8:6 led2 speed led 2 speed select 000 = active for 10base-t link 001 = reserved 010 = reserved 011 = reserved 100 = reserved 101 = active for 100base-x 110 = off 111 = reserved 24.5:3 led1 speed led 1 speed select 000 = active for 10base-t link 001 = reserved 010 = reserved 011 = reserved 100 = reserved 101 = active for 100base-x 110 = off 111 = reserved 24.2:0 led0 speed led 0 speed select 000 = active for 10base-t link 001 = reserved 010 = reserved 011 = reserved 100 = reserved 101 = active for 100base-x 110 = off 111 = reserved
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 46 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.11.3 led polarity the polarity of the led in the active state can be set through register 25.14:12. 2.11.4 stretching and blinking some of the statuses can be pulse stretched. pulse stre tching is necessary because t he duration of these status events might be too short to be observable on the leds. the pulse stretch duration can be programmed via reg- ister 24.14:12. the default pulse stretch duration is set to 170 to 340 ms. the pulse stretch duration applies to all applicable leds. some of the statuses indicate multip le events by blinking leds. the blin k period can be programmed via register 24.11:9. the default blink period is set to 84 ms. the blink rate applies to all applicable leds. table 25: led active polarity bits field description 25.14 invled2 invert led2. this bit controls the active level of the led2 pin. 0 = active low led2 1 = active high led2 25.13 invled1 invert led1. this bit controls the active level of the led1 pin. 0 = active low led1 1 = active high led1 25.12 invled0 invert led0. this bit controls the active level of the led0 pin. 0 = active low led0 1 = active high led0
functional description automatic and manual impedance calibration copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 47 2.12 automatic and manual impedance calibration 2.12.1 mac interface calibration circuit the auto calibration is available for the mac interface i/o s. the phy runs the automat ic calibration circuit with a 49 ohm impedance target by default after hardware reset. other impedance targets are available by changing the impedance target and restarting the auto calibration through register writes . individual nmos and pmos output transistors could be controlled for 38 to 80 ohm targets in various increments. manual nmos and pmos settings are avai lable if the automatic calibration is not desired. if the pcb traces are different from 50 ohms, the output im pedance of the mac interface i/o buffe rs can be programmed to match the trace impedance. users can adjust the nmos and pmos dr iver output strengths to pe rfectly match the transmis- sion line impedance and eliminate reflections completely. note the crs, col, and rx_er pins are not calibrated. 2.12.2 mac interface calibrat ion register definitions if register 29 = 0x000a, then register 30 is defined as follows: table 26: register 30 page 10 - mac interface calibration definitions reg bit function setting d escription mode hw reset sw reset 15 restart calibration 0 = normal 1 = restart bit 15 is a self-clearing register. calibration will start once the register is cleared. r/w 0 retain 14 calibration com- plete 1 = calibration complete 0 = calibration in progress ro 0 retain 13 reserved 0 r/w 0 retain 12:8 pmos value 00000 = all fingers off ... 11111 = all fi ngers on the automatic calibrated values are stored here after calibration completes. once the latch bit is set to 1, the new cal- ibration value is written. the automatic cali- brated value is lost. r/w auto cal- ibrated value retain 7 reserved 0 r/w 0 retain 6 latch 1 = latch in new value. this bit self clears. (used for manual settings) r/w, sc 0retain
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 48 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.12.3 changing auto calibration targets the phy runs the automatic calibrati on circuit with a 49 ohm impedance target by default after hardware reset. other impedance targets are available by changing the impedance target and restar ting the auto calibration through register writes. to change the auto calibration targets, write to the following registers: write to register 29 = 0x000b write to register 30, bit 6:4 = ppp (write new pmos target value) write to register 30, bit 2:0 = nnn (write new nmos target value) write to register 29 = 0x000a write to register 30 = 0x8000 (restarts t he auto calibration with the new target) example: to set the approximate 54 ohm auto calibration target, write the following: reg29 = 0x000b reg30, bit 6:4 = ? 011? and bit 2:0 = ? 011? reg29 = 0x000a reg30 = 0x8000 2.12.4 manual settings to the calibration registers to use manual calibration, write to the following registers: write to register 29 = 0x000a write to register 30 = b'000p pppp 01 1n nnnn -- adjusts pmos strength 5 pmos/nmos select 1 = pmos value is written when latch is set to 1 0 = nmos value is written when latch is set to 1 r/w 0 retain 4:0 nmos value 00000 = all fingers off ... 11111 = all fingers on the automatic calibrated values are stored here after calibration completes. once the latch bit is set to 1, the new cal- ibration value is written. the automatic cali- brated value is lost. r/w auto cal- ibrated value retain table 26: register 30 page 10 - mac interface calibration definitions (continued) reg bit function setting description mode hw reset sw reset
functional description automatic and manual impedance calibration copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 49 write to register 30 = b'000p pppp 010n nnnn -- adjusts nmos strength where ppppp is the 5 bit value for the pmos strength. where nnnnn is the 5 bit value for the nmos strength. the value of ppppp or nnnnn will depend on your board. the ?11111? value enables all fingers for maximum drive strength, for minimum impedance. the ?00000? value tu rns all fingers off for minimum drive strength, for max- imum impedance. use a scope to monito r the rx_clk pin close to the destinat ion. start with the default auto-cal- ibrated value and move in each direction to see how it affects signal in tegrity on your board. example: the automatic calibration has a 49 ohm target, but if the mii trace impedance on board was 60 ohms, you see reflections from a scope capt ure taken at the destination. see figure 14 . after manual calibration, you see that the reflections are eliminated in figure 15 . figure 12 and figure 13 display the trend lines for 1.8v and 2. 5v pmos and nmos impedance settings. note: the trend lines displayed in figure 12 and figure 13 use nominal values and may vary in production. figure 12: pmos output impedance (1.8v, 2.5v) trend lines (tbd) 0 10 20 30 40 50 60 70 80 90 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pmos register value (decimal) impedance settings (ohms) 2.5v 3.3v
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 50 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver figure 13: nmos output impedance (1.8v, 2.5v) trend lines (tbd) example: the automatic calibration has a 50 ohm target, but if the mii trace impedance on board was 60 ohms, you see reflections from a scope capture taken at the destination. refer to figure 14 . after manual calibration, you see that the reflections are eliminated as in figure 15 . figure 14: signal reflections, using the 50 ohm setting, 60 ohm line 0 10 20 30 40 50 60 70 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nmos register value decimal impedance settings (ohms) 2.5v 3.3v
functional description automatic and manual impedance calibration copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 51 figure 15: clean signal after manual calibration for the 60 ohm
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 52 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2.13 crc error counter the crc counter, normally found in macs, is available in the 88e3015/88E3018 device. the error counter fea- ture is enabled through register writes and th e counter is stored in an eight bit register. 2.13.1 enabling the crc error counter 2.13.1.1 enabling counter write to the following regist ers will enable both counters. register 29: 0x0009 (points to page 9 of register 30) register 30: 0x0001 (enables crc error counter) 2.13.1.2 disabling a nd clearing counter write to the following register wil l disable and clear both counters. register 29: 0x0009 (points to page 9 of register 30) register 30: 0x0000 (disable and clear crc error) 2.13.1.3 reading counter content to read the crc counter, write to the following registers. register 29: 0x0009 (points to page 9 of register 30) register 30: bits 15:8 (crc error count is stored in these bits) the counter does not clear on a read command. to clear the crc error counter, disable and enable the counters. see page 9 of register 30 for details.
functional description ieee 1149.1 controller copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 53 2.14 ieee 1149.1 controller the 88E3018 supports the ieee1149.1 test access port and boundary scan. the 88e30 15 does not support this feature. the ieee 1149.1 standard defines a test access port and bounda ry-scan architecture for digital integrated circuits and for the digital portions of mixed analog/digital integrated circuits. the standard provides a solution for testing assembled pr inted circuit boards and other products based on highly complex digital integrated circuits and high- density surface-mounting assembly techniques. the 88E3018 device implements six basic instructions: by pass, sample/preload, extest, clamp, high-z, and id code. upon reset, id_code instruction is se lected. the instruction opcodes are shown in ta b l e 2 7 . the 88E3018 device reserves 5 pins called the test access port (tap) to provide test access test mode select input (tms), test clock input (tck), test data input (tdi), and test data output (tdo), and test reset input (trstn). to ensure race-free operation all input and output data is synchronous to the test clock (tck). tap input signals (tms and tdi) are clocked into the test logic on the rising edge of tck, while output signal (tdo) is clocked on the falling edge. fo r additional details refer to the ieee 1149.1 boundary scan architecture document. 2.14.1 bypass instruction the bypass instruction uses the bypass register. the bypass register contains a single shift-register stage and is used to provide a minimum length serial path between the tdi and tdo pins of the 88E3018 device. this allows rapid movement of test data to and fr om other testable devices in the system. the extest instruction allows circuitry external to the 88E3018 device (typically the board interconnections) to be tested. prior to executing the extest in struction, the first test stimulus to be applied is shifted into the boundary- scan registers using the sample/preload instruction. thus, when the change to the extest instruction takes place, known data is driven immediately from the 88E3018 device to its external connections. 2.14.2 sample/preload instruction the sample/preload instruction allows scanning of the bound ary-scan register without causing interference to the normal operation of the 88E3018 device. two functions ar e performed when this instruction is selected: sample and preload. table 27: tap controller op codes instruction opcode extest 00000000 sample/preload 00000001 clamp 00000010 high-z 00000011 bypass 11111111 id code 00000100
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 54 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver sample allows a snapshot to be taken of the data flowing from the system pins to the on-chip test logic or vice versa, without interfering with normal operation. the snapshot is taken on the rising edge of tck in the capture- dr controller state, and the data can be viewed by shifting through the component's tdo output. while sampling and shifting data out through tdo for observation, preload allows an initial data pattern to be shifted in through tdi and to be placed at the latched pa rallel output of the boundary- scan register cells that are connected to system output pins. this ensures that know n data is driven through the system output pins upon entering the extest instructi on. without preload, indeterminate data woul d be driven until the first scan sequence is complete. the shifting of data for the sample and preload phases can occur simultaneously. while data capture is being shifted out, the preload data can be shifted in. one scan chain is available for the 88E3018 devices. table 28: 88E3018 boundary scan chain order pin i/o mdio output enable mdio output mdio input mdc input (rgmii) output enable rx_ctrl output rxd[0] output rxd[1] output rx_clk output rxd[2] output rxd[3] output txd[0] input txd[1] input tx_clk input txd[2] input txd[3] input tx_ctrl input config[0] input config[1] input config[2] input config[3] input led[0] output enable led[0] output led[1] output enable led[1] output led[2] output enable led[2] output coman input reset input sigdet input
functional description ieee 1149.1 controller copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 55 2.14.3 extest instruction the extest instruction allows circuitry external to the phy (typically the boar d interconnections) to be tested. prior to executing the extest instru ction, the first test stimulus to be applied is shifted into the boundary-scan registers using the sample/preload instruction. thus, when the change to the extest instruction takes place, known data is driven immediately from the ph y to its external connections. 2.14.4 the clamp instruction the clamp instruction allows the state of the signals driv en from component pins to be determined from the bound- ary-scan register while the bypass regist er is selected as the serial path between tdi and tdo. the signals driven from the component pins will not change while the clamp instruction is selected. 2.14.5 the high-z instruction the high-z instruction places the component in a state in which all of its system logic outputs are placed in an inactive drive state (e.g., high imped ance). in this state, an in-circuit te st system may drive signals onto the con- nections normally driven by a component output witho ut incurring the risk of damage to the component. 2.14.6 id code instruction the id code contains the manufacturer identity, part and version. (mii) output enable rx_er output crs output col output table 29: id code version part number manufacturer identity bit 31 to 28 bit 27 to 12 bit 11 to 1 0 0000 0000 0000 0010 0001 001 1110 1001 1 table 28: 88E3018 boundary scan chain order (continued) pin i/o
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 56 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver section 3. register description the ieee defines only 32 registers address space for the phy. in order to extend the number of registers address space available a paging mechanism is used. for register a ddress 30, register 29 bits 4 to 0 are used to specify the page. there is no paging for registers 1 and 28. in this document, the short hand used to specify the registers take the form re gister_page.bit:bit, register_page.bit, register.bit:bit, or register.bit. for example: register 30 page 9 bits 15 to 8 are specified as 30_9.15:8. register 30 page 9 bit 0 is specified as 30_9.0. register 2 bit 3 to 0 is specified as 2.3:0. note that in this context the setting of t he page register (register 29) has no effect. register 2 bit 3 is specified as 2.3.
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 57 table 30 defines the register types used in the register map. table 30: register types type description lh register field with latching high function. if status is high, then the register is set to a one and remains set until a read operation is performed through the management interface or a reset occurs. ll register field with latching low function. if status is low, then the register is cleared to zero and remains zero until a read operation is performed through the management interface or a reset occurs. retain value written to the register field does take effect without a software reset, and the register maintains its value after a software reset. res reserved for future use. all reserved bits are read as zero unless otherwise noted. ro read only. roc read only clear. after read, register field is cleared to zero. r/w read and write with initial value indicated. rwc read/write clear on read. all bits are readable and writable. after reset or after the regis- ter field is read, register field is cleared to zero. sc self-clear. writing a one to this register causes the desired function to be immediately executed, then the register field is automatically cleared to zero when the function is complete. update value written to the register field does not take effect until soft reset is executed; however, the written value can be read even before the software reset. wo write only. reads to this type of register field return undefined data.
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 58 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 31: register map register name register address table and page phy control register register 0 table 32, p. 59 phy status register register 1 table 33, p. 61 phy identifier register 2 table 34, p. 63 phy identifier register 3 table 35, p. 63 auto-negotiation advertisement register register 4 table 36, p. 64 link partner ability register (base page) register 5 table 37, p. 66 link partner ability register (next page) register 5 table 38, p. 67 auto-negotiation expansion register register 6 table 39, p. 68 next page transmit register register 7 table 40, p. 69 link partner next page register register 8 table 41, p. 69 phy specific control register register 16 table 42, p. 70 phy specific status register register 17 table 43, p. 72 phy interrupt enable register 18 table 44, p. 73 phy interrupt status register 19 table 45, p. 75 phy interrupt port summary register 20 table 46, p. 76 receive error counter register 21 table 47, p. 76 led parallel select register register 22 table 48, p. 77 phy led control register register 24 table 49, p. 79 phy manual led override register 25 table 50, p. 80 vct? register for mdip/n[0] pins register 26 table 51, p. 81 vct? register for mdip/n[1] pins register 27 table 52, p. 82 phy specific control register ii register 28 table 53, p. 83 test mode select register 29 table 54, p. 84 crc status register register 30_9 table 55, p. 84 mac interface output impedance calibration override register 30_10 table 56, p. 85 mac interface output impedance target register 30_11 table 57, p. 86
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 59 table 32: phy control register register 0 bits field mode hw rst sw rst description 15 swreset r/w, sc 0x0 0x0 phy software reset writing a 1 to this bit causes the phy state machines to be reset. when the reset operation is done, this bit is cleared to 0 automatically. the reset occurs immedi- ately. 0 = normal operation 1 = phy reset 14 loopback r/w 0x0 retain enable loopback mode when loopback mode is activated, the transmitter data presented on txd is looped back to rxd internally. the phy has to be in forced 10 or 100 mbps mode. auto- negotiation must be disabled. 0 = disable loopback 1 = enable loopback 13 speedlsb r/w 0x1 update speed selection (lsb) when a speed change occurs, the phy drops link and tries to determine speed when auto-negotiation is on. a write to this register bit has no effect unless any one of the following also occurs: software reset is a sserted (bit 15) or power down (bit 11) transitions from power down to nor- mal operation. 0 = 10 mbps 1 = 100 mbps 12 anegen r/w 0x1 update auto-negotiation enable a write to this register bit has no effect unless any one of the following also occurs: software reset is asserted (bit 15, above), power down (bit 11, below), or the phy transitions from power down to normal operation. if the anegen bit is set to 0, the speed and duplex bits of the phy control register (register 0) take effect. if the anegen bit is set to 1, speed and duplex advertise- ment is found in the auto-negotiation advertisement register (register 4). 0 = disable auto-negotiation process 1 = enable auto-negotiation process
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 60 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 11 pwrdwn r/w 0x0 retain power down mode when the port is switched from power down to normal operation, software reset and restart auto-negotiation are performed even when bits reset (bit 15, above) and restart auto-negotiation (bit 9, below) are not set by the user. 0 = normal operation 1 = power down 10 isolate r/w 0x0 retain isolate mode 0 = normal operation 1 = isolate 9 restartaneg r/w, sc 0x0 self clear restart auto-negotiation auto-negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit is set. 0 = normal operation 1 = restart auto-negotiation process 8 duplex r/w 0x1 update duplex mode selection a write to this registers has no effect unless any one of the following also occurs: software reset is asserted (b it 15), power down (bit 11), or transitions from power down to normal operation. 0 = half-duplex 1 = full-duplex 7 coltest r/w 0x0 retain collision test mode - this applies to e3010 only. 0 = disable col signal test 1 = enable col signal test 6 speedmsb ro always 0 always 0 speed selection mode (msb) will always be 0. 0 = 100 mbps or 10 mbps 5 unidirectional enable r/w 0x0 retain 0 = enable transmit direction only when valid link is established. 1 = enable transmit direction regardless of valid link if register 0.12 = 0 and 0.8 = 1. otherwise enable transmit direction only when valid link is established. 4:0 reserved ro always 0 always 0 will always be 0. table 32: phy control register (continued) register 0 bits field mode hw rst sw rst description
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 61 table 33: phy status register register 1 bits field mode hw rst sw rst description 15 100t4 ro always 0 always 0 100base-t4 this protocol is not available. 0 = phy not able to perform 100base-t4 14 100fdx ro always 1 always 1 100base-t and 100base-x full-duplex 1 = phy able to perform full-duplex 13 100hdx ro always 1 always 1 100base-t and 100base-x half-duplex 1 = phy able to perform half-duplex 12 10fdx ro always 1 always 1 10base-t full-duplex 1 = phy able to perform full-duplex 11 10hpx ro always 1 always 1 10base-t half-duplex 1 = phy able to perform half-duplex 10 100t2fdx ro always 0 always 0 100base-t2 full-duplex. this protocol is not available. 0 = phy not able to perform full-duplex 9 100t2hdx ro always 0 always 0 100base-t2 half-duplex this protocol is not available. 0 = phy not able to perform half-duplex 8 extdstatus ro always 0 always 0 extended status 0 = no extended status information in register 15 7 unidirectional ability ro always 1 always 1 1 = phy able to transmit from media independent inter- face regardless of whether the phy has determined that a valid link has been established 6 mfpresup ro always 1 always 1 mf preamble suppression mode must be always 1. 1 = phy accepts management frames with preamble suppressed 5 anegdone ro 0x0 0x0 auto-negotiation complete 0 = auto-negotiation process not completed 1 = auto-negotiation process completed 4 remotefault ro, lh 0x0 0x0 remote fault mode 0 = remote fault condition not detected 1 = remote fault condition detected 3 anegable ro always 1 always 1 auto-negotiation ability mode 1 = phy able to perform auto-negotiation
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 62 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2 link ro, ll 0x0 0x0 link status mode this register indicates when link was lost since the last read. for the current link status, either read this register back-to-back or read rtlink (17.10). 0 = link is down 1 = link is up 1 jabberdet ro, lh 0x0 0x0 jabber detect 0 = jabber condition not detected 1 = jabber condition detected 0 extdreg ro always 1 always 1 extended capability mode. 1 = extended register capabilities table 33: phy status register (continued) register 1 bits field mode hw rst sw rst description
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 63 table 34: phy identifier register 2 bits field mode hw rst sw rst description 15:0 organization- ally unique identifier bit 3:18 ro 0x0141 0x0141 marvell ? oui is 0x005043 0000 0000 0101 0000 0100 0011 ^ ^ bit 1............................................bit 24 register 2.[15:0] show bits 3 to 18 of the oui. 101000001 ^ ^ bit 3........................bit 18 table 35: phy identifier register 3 bits field mode hw rst sw rst description 15:10 oui lsb ro always 000011 always 000011 organizationally unique identifier bits 19:24 00 0011 ^..........^ bit 19...bit 24 9:4 modelnum ro always 100010 always 100010 model number = 100010 3:0 revnum ro varies varies revision number contact marvell ? faes for information on the device revision number.
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 64 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 36: auto-negotiation advertisement register register 4 bits field mode hw rst sw rst description 15 anegad nxtpage r/w 0x0 retain next page 0 = not advertised 1 = advertise values programmed into the auto-negotiation adver- tisement register have no effect unless auto-negotia- tion is restarted (restartaneg 0.9) or link goes down. 14 ack ro always 0 always 0 must be 0. 13 anegad refault r/w 0x0 retain remote fault mode 0 = do not set remote fault bit 1 = set remote fault bit values programmed into the auto-negotiation adver- tisement register have no effect unless auto-negotia- tion is restarted (restartaneg 0.9) or link goes down. 12 reserved r/w 0x0 retain must be 0. reserved bits are r/w to allow for forward compatibility with future ieee standards. values programmed into the auto-negotiation adver- tisement register have no effect unless auto-negotia- tion is restarted (restartaneg 0.9) or link goes down. 11 anegad asym- metric pause r/w 0x0 retain asymmetric pause mode 0 = asymmetric pause not implemented 1 = asymmetric pause implemented values programmed into the auto-negotiation adver- tisement register have no effect unless auto-negotia- tion is restarted (restartaneg 0.9) or link goes down. 10 anegad pause r/w 0x0 retain pause mode 0 = mac pause not implemented 1 = mac pause implemented values programmed into the auto-negotiation adver- tisement register have no effect unless auto-negotia- tion is restarted (restartaneg 0.9) or link goes down. 9 anegad 100t4 r/w 0x0 r etain 100base-t4 mode 0 = not capable of 100base-t4 must be 0. 8 anegad 100fdx r/w 0x1 retain 100base-tx full-duplex mode 0 = not advertised 1 = advertise values programmed into the auto-negotiation adver- tisement register have no effect unless auto-negotia- tion is restarted (restartaneg 0.9) or link goes down.
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 65 7 anegad 100hdx r/w 0x1 retain 100base-tx half-duplex mode 0 = not advertised 1 = advertise values programmed into the auto-negotiation adver- tisement register have no effect unless auto-negotia- tion is restarted (restartaneg 0.9) or link goes down. 6 anegad 10fdx r/w 0x1 retain 10base-tx full-duplex mode 0 = not advertised 1 = advertise values programmed into the auto-negotiation adver- tisement register have no effect unless auto-negotia- tion is restarted (restartaneg 0.9) or link goes down. 5 anegad 10hdx r/w 0x1 retain 10base-tx half-duplex mode 0 = not advertised 1 = advertise values programmed into the auto-negotiation adver- tisement register have no effect unless auto-negotia- tion is restarted (restartaneg 0.9) or link goes down. 4:0 anegad selec- tor r/w always 0x01 always 0x01 selector field mode 00001 = 802.3 table 36: auto-negotiation advertisement register (continued) register 4 bits field mode hw rst sw rst description
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 66 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 37: link partner ability register (base page) register 5 bits field mode hw rst sw rst description 15 lpnxt page ro 0x0 0x0 next page mode base page will be overwritten if next page is received and if reg8nxtpg (16.12) is disabled. when reg8nxtpg (16.12) is enabled, then next page is stored in the link partner next page register, and the link partner ability register holds the base page. received code word bit 15 0 = link partner not capable of next page 1 = link partner capable of next page 14 lpack ro 0x0 0x0 acknowledge received code word bit 14 0 = link partner did not receive code word 1 = link partner received link code word 13 lpremote fault ro 0x0 0x0 remote fault received code word bit 13 0 = link partner has not detected remote fault 1 = link partner detected remote fault 12:5 lptechable ro 0x00 0x00 technology ability field received code word bit 12:5 4:0 lpselector ro 0x00 0x00 selector field received code word bit 4:0
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 67 table 38: link partner ability register (next page) register 5 bits field mode hw rst sw rst description 15 lpnxtpage ro -- -- next page mode base page will be overwritten if next page is received and if reg8nxtpg (16.12) is disabled. when reg8nxtpg (16.12) is enabled, then next page is stored in the link partner next page register, and link partner ability register holds the base page. received code word bit 15 14 lpack ro -- -- acknowledge received code word bit 14 13 lpmessage ro -- -- message page received code word bit 13 12 lpack2 ro -- -- acknowledge 2 received code word bit 12 11 lptoggle ro -- -- toggle received code word bit 11 10:0 lpdata ro -- -- message/unformatted field received code word bit 10:0
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 68 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 39: auto-negotiation expansion register register 6 bits field mode hw rst sw rst description 15:5 reserved ro always 0x000 always 0x000 reserved. the auto-negotiation expansion register is not valid until the anegdone (1.5) indicates completed. 4 parfaultdet ro/lh 0x0 0x0 parallel detection level 0 = a fault has not been detected via the parallel detec- tion function 1 = a fault has been detected via the parallel detection function 3 lpnxtpg able ro 0x0 0x0 link partner next page able 0 = link partner is not next page able 1 = link partner is next page able 2 localnxtpg able ro always 0x1 always 0x1 local next page able this bit is equivalent to anegable. 1 = local device is next page able 1 rxnewpage ro/lh 0x0 0x0 page received 0 = a new page has not been received 1 = a new page has been received 0 lpanegable ro 0x0 0x0 link partner auto-negotiation able 0 = link partner is not auto-negotiation able 1 = link partner is auto-negotiation able
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 69 table 40: next page transmit register register 7 bits field mode hw rst sw rst description 15 txnxtpage r/w 0x0 0x0 a write to the next page transmit register implicitly sets a variable in the auto-negotiation state machine indicating that the next page has been loaded. transmit code word bit 15 14 reserved ro 0x0 0x0 reserved transmit code word bit 14 13 txmessage r/w 0x1 0x1 message page mode transmit code word bit 13 12 txack2 r/w 0x0 0x0 acknowledge2 transmit code word bit 12 11 txtoggle ro 0x0 0x0 toggle transmit code word bit 11 10:0 txdata r/w 0x001 0x001 message/unformatted field transmit code word bit 10:0 table 41: link partner next page register register 8 bits field mode hw rst sw rst description 15 rxnxtpage ro 0x0 0x0 if reg8nxtpg (16.12) is enabled, then next page is stored in the link partner next page register; otherwise, the link partner next page register is cleared to all 0s. received code word bit 15 14 rxack ro 0x0 0x0 acknowledge received code word bit 14 0 = link partner not capable of next page 1 = link partner capable of next page 13 rxmessage ro 0x0 0x0 message page received code word bit 13 12 rxack2 ro 0x0 0x0 acknowledge 2 received code word bit 12 11 rxtoggle ro 0x0 0x0 toggle received code word bit 11 10:0 rxdata ro 0x000 0x000 message/unformatted field received code word bit 10:0
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 70 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 42: phy specific control register register 16 bits field mode hw rst sw rst description 15 reserved r/w 0x0 retain 14 edet r/w 0x0 retain energy detect 0 = disable 1 = enable with sense and pulse enable with sense only is not supported 13 disnlp check r/w 0x0 0x0 disable normal linkpulse check linkpulse check and generation disable have no effect, if auto-negotiation is enabled locally. 0 = enable linkpulse check 1 = disable linkpulse check 12 reg8nxtpg r/w 0x0 0x0 enable the link partner next page register to store next page. if set to store next page in the link partner next page register (register 8), then 802.3u is violated to emulate 802.3ab. 0 = store next page in the link partner ability register (base page) register (register 5). 1 = store next page in the link partner next page regis- ter. 11 disnlpgen r/w 0x0 0x0 disable linkpulse generation. linkpulse check and generation disable have no effect, when auto-negotiation is enabled locally. 0 = enable linkpulse generation 1 = disable linkpulse generation 10 reserved r/w 0x0 0x0 set to 0 9 disscrambler r/w 0x0 retain disable scrambler if either 100base-fx or 10 base-t forced mode is selected, then the scrambler is disabled at hardware reset. however, when 100base -tx is selected, this reg- ister bit equals 0. 0 = enable scrambler 1 = disable scrambler 8 disfefi r/w 0x1 retain disable fefi fefi is automatically disabled regardless of the state of this bit if copper mode is selected. 0 = enable fefi 1 = disable fefi
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 71 7 extddistance r/w 0x0 0x0 enable extended distance when using cable exceeding 100 meters, the 10base- t receive threshold must be lowered in order to detect incoming signals. 0 = normal 10base-t receive threshold 1 = lower 10base-t receive threshold 6sigdet polar- ity r/w 0x0 update 0 = sigdet active high 1 = sigdet active low 5:4 automdi[x] r/w see desc. update mdi/mdix crossover during hardware reset register 16.5:4 defaults as fol- lows ena_xc 16.5:4 0 00 1 11 this setting can be changed by writing to these bits fol- lowed by software reset. 00 = transmit on pins mdip/n[0], receive on pins mdip/n[1] 01 = transmit on pins mdip/n[1], receive on pins mdip/n[0] 1x = enable automatic crossover 3 reserved r/w 0x0 retain 2 sqe test r/w 0x0 retain sqe test is automatically disabled in full duplex mode 0 = disable sqe test 1 = enable sqe test 1 autopol r/w 0x0 0x0 polarity reversal if automatic polarity is disabled, then the polarity is forced to be normal in 10base-t mode. polarity rever- sal has no effect in 100base-tx mode. this bit only controls polarity correction at the inputs. the output polarity is not programmable. 0 = enable automatic polarity reversal 1 = disable automatic polarity reversal 0 disjabber r/w 0x0 0x0 disable jabber jabber has no effect in full-duplex or in 100base-x mode. 0 = enable jabber function 1 = disable jabber function table 42: phy specific control register (continued) register 16 bits field mode hw rst sw rst description
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 72 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 43: phy specific status register register 17 bits field mode hw rst sw rst description 15 reserved ro 0x0 0x0 0 14 resspeed ro 0x1 retain resolved speed the values are updated after the completion of auto- negotiation. the registers retain their values during soft- ware reset. this bit is valid only after the resolved bit 11 is set. 0 = 10 mbps 1 = 100 mbps. 13 resduplex ro 0x1 retain resolved duplex mode the values are updated after the completion of auto- negotiation. the registers retain their values during soft- ware reset. this bit is valid only after the resolved bit 11 is set. 0 = half-duplex 1 = full-duplex 12 rcvpage ro, lh 0x0 0x0 page receive mode 0 = page not received 1 = page received 11 resolved ro 0x0 0x0 speed and duplex resolved. speed and duplex bits (14 and 13) are valid only after the resolved bit is set. the resolved bit is set when auto-negotiation has resolved the highest common capabilities or auto-negotiation is disabled. 0 = not resolved 1 = resolved 10 rtlink ro 0x0 0x0 link (real time) 0 = link down 1 = link up 9:7 reserved res always 000 always 000 always 000. 6 mdi/mdix ro 0x0 0x0 mdi/mdix crossover status 0 = transmit on pins txp/txn, receive on pins rxp/ rxn 1 = transmit on pins rxp/rxn, receive on pins txp/ txn 5 reserved res always 0 always 0 always 0. 4 sleep ro 0x0 0x0 energy detect status 0 = chip is not in sleep mode (active) 1 = chip is in sleep mode (no wire activity)
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 73 3:2 reserved res always 00 always 00 always 00. 1 rtpolarity ro 0x0 0x0 polarity (real time) 0 = normal 1 = reversed 0 rtjabber ro 0x0 retain jabber (real time) 0 = no jabber 1 = jabber table 44: phy interrupt enable register 18 bits field mode hw rst sw rst description 15 reserved r/w 0x0 retain 0 14 speedinten r/w 0x0 retain speed changed interrupt enable 0 = interrupt disable 1 = interrupt enable 13 duplexinten r/w 0x0 retain duplex changed interrupt enable 0 = interrupt disable 1 = interrupt enable 12 rxpageinten r/w 0x0 retain page received interrupt enable 0 = interrupt disable 1 = interrupt enable 11 anegdone inten r/w 0x0 retain auto-negotiation completed interrupt enable 0 = interrupt disable 1 = interrupt enable 10 linkinten r/w 0x0 retain link status changed interrupt enable 0 = interrupt disable 1 = interrupt enable 9 symerrinten r/w 0x0 retain symbol error interrupt enable 0 = interrupt disable 1 = interrupt enable 8 flscrsinten r/w 0x0 retain false carrier interrupt enable 0 = interrupt disable 1 = interrupt enable 7 fifoerrint r/w 0x0 retain fifo over/underflow interrupt enable 0 = interrupt disable 1 = interrupt enable table 43: phy specific status register (continued) register 17 bits field mode hw rst sw rst description
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 74 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 6 mdi[x]inten r/w 0x0 0x0 mdi/mdix crossover changed interrupt enable 0 = interrupt disable 1 = interrupt enable 5 reserved res 0x0 retain must be 0. 4 edetinten r/w 0x0 retain energy detect interrupt enable 0 = disable 1 = enable 3:2 reserved res 0x0 retain must be 00. 1 polarityinten r/w 0x0 retain polarity changed interrupt enable 0 = interrupt disable 1 = interrupt enable 0 jabberinten r/w 0x0 retain jabber interrupt enable 0 = interrupt disable 1 = interrupt enable table 44: phy interrupt enable register 18 bits field mode hw rst sw rst description
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 75 table 45: phy interrupt status register 19 bits field mode hw rst sw rst description 15 reserved ro 0x0 0x0 0 14 speedint ro, lh 0x0 0x0 speed changed 0 = speed not changed 1 = speed changed 13 duplexint ro, lh 0x0 0x0 duplex changed 0 = duplex not changed 1 = duplex changed 12 rxpageint ro, lh 0x0 0x0 0 = page not received 1 = page received 11 anegdoneint ro, lh 0x0 0x0 auto-negotiation completed 0 = auto-negotiation not completed 1 = auto-negotiation completed 10 linkint ro, lh 0x0 0x0 link status changed 0 = link status not changed 1 = link status changed 9 symerrint ro, lh 0x0 0x0 symbol error 0 = no symbol error 1 = symbol error 8 flscrsint ro, lh 0x0 0x0 false carrier 0 = no false carrier 1 = false carrier 7 fifoerrint ro, lh 0x0 0x0 fifo over /underflow error 0 = no over/underflow error 1 = over/underflow error 6 mdimdixint ro, lh 0x0 0x0 mdi/mdix crossover changed 0 = mdi/mdix crossover not changed 1 = mdi/mdix crossover changed 5 reserved ro always 0 always 0 always 0 4 edetchg ro, lh 0x0 0x0 energy detect changed 0 = no change 1 = changed 3:2 reserved ro always 00 always 00 always 00 1 polarityint ro 0x0 0x0 polarity changed 0 = polarity not changed 1 = polarity changed
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 76 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 0 jabberint ro, lh 0x0 0x0 jabber mode 0 = no jabber 1 = jabber table 46: phy interrupt port summary register 20 bits field mode hw rst sw rst description 15:0 reserved ro 0x0000 0x0000 table 47: receive error counter register 21 bits field mode hw rst sw rst description 15:0 rxerrcnt ro 0x0000 0x0000 receive error count this register counts receive errors on the media inter face. when the maximum receive error count reaches 0xffff, the counter will roll over. table 45: phy interrupt status (continued) register 19 bits field mode hw rst sw rst description
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 77 table 48: led parallel select register register 22 bits field mode hw rst sw rst description 15:12 reserved r/w 0x4 retain 11:8 led2 r/w 0xa retain led2 control. this is a global setting. 0000 = colx 0001 = error 0010 = duplex 0011 = duplex/colx 0100 = speed 0101 = link 0110 = tx 0111 = rx 1000 = act 1001 = link/rx 1010 = link/act 1011 = act (blink mode) 1100 = tx (blink mode) 1101 = rx (blink mode) 1110 = interrupt 1111 = force to 1 (inactive) 7:4 led1 r/w 0x4 retain led1 control. this is a global setting. 0000 = colx 0001 = error 0010 = duplex 0011 = duplex/colx 0100 = speed 0101 = link 0110 = tx 0111 = rx 1000 = act 1001 = link/rx 1010 = link/act 1011 = act (blink mode) 1100 = tx (blink mode) 1101 = rx (blink mode) 1110 = colx (blink mode) 1111 = force to 1 (inactive)
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 78 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 3:0 led0 r/w 0x4 retain led0 control. this is a global setting. 0000 = colx 0001 = error 0010 = duplex 0011 = duplex/colx 0100 = speed 0101 = link 0110 = tx 0111 = rx 1010 = link/act 1011 = act (blink mode) 1100 = tx (blink mode) 1101 = rx (blink mode) 1110 = colx (blink mode) 1111 = force to 1 (inactive) table 48: led parallel select register (continued) register 22 bits field mode hw rst sw rst description
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 79 table 49: phy led control register register 24 bits field mode hw rst sw rst description 15 reserved ro always 0 always 0 must be 0. 14:12 pulsestretch r/w 0x4 retain pulse stretch duration. this is a global setting. 000 = no pulse stretching 001 = 21 ms to 42 ms 010 = 42 ms to 84 ms 011 = 84 ms to 170 ms 100 = 170 ms to 340 ms 101 = 340 ms to 670 ms 110 = 670 ms to 1.3s 111 = 1.3s to 2.7s 11:9 blinkrate r/w 0x1 retain blink rate. this is a global setting. 000 = 42 ms 001 = 84 ms 010 = 170 ms 011 = 340 ms 100 = 670 ms 101 to 111 = reserved 8:6 led2 speed r/w 0x0 retain led 2 speed select 000 = active for 10base-t link 001 = reserved 010 = reserved 011 = reserved 100 = reserved 101 = active for 100base-x 110 = reserved 111 = reserved 5:3 led1 speed r/w 0x0 retain led 1 speed select 000 = active for 10base-t link 001 = reserved 010 = reserved 011 = reserved 100 = reserved 101 = active for 100base-x 110 = reserved 111 = reserved
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 80 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 2:0 led0 speed r/w 0x5 retain led 0 speed select 000 = active for 10base-t link 001 = reserved 010 = reserved 011 = reserved 100 = reserved 101 = active for 100base-x 110 = reserved 111 = reserved table 50: phy manual led override register 25 bits field mode hw rst sw rst description 15 reserved r/w 0x0 retain 0 14 invled2 r/w 0x0 retain invert led2. this bit controls the active level of the led2 pin. 0 = active low led2 1 = active high led2 13 invled1 r/w 0x0 retain invert led1. this bit controls the active level of the led1 pin. 0 = active low led1 1 = active high led1 12 invled0 r/w 0x0 retain invert led0. this bit controls the active level of the led0 pin. 0 = active low led0 1 = active high led0 11:6 reserved r/w 0x00 retain 000000 5:4 forceled2 r/w 0x0 retain 00 = normal 01 = blink[1] 10 = led off 11 = led on 3:2 forceled1 r/w 0x0 retain 00 = normal 01 = blink 10 = led off 11 = led on 1:0 forceled0 r/w 0x0 retain 00 = normal 01 = blink 10 = led off 11 = led on table 49: phy led control register (continued) register 24 bits field mode hw rst sw rst description
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 81 table 51: vct? register for mdip/n[0] pins register 26 bits field mode hw rst sw rst description 15 envct r/w, sc 0x0 0x0 enable vct 0 = vct completed 1 = run vct after running vct once, bit 15 = 0 indicates vct com- pleted. the cable status is reported in the vcttst bits in regis- ters 26 and 27. refer to the virtual cable tester ? feature. 14:13 vcttst ro 0x0 retain vct test status these vct test status bits are valid after completion of vct. 00 = valid test, normal cable (no short or open in cable) 01 = valid test, short in cable (impedance < 33 ohm) 10 = valid test, open in cable (impedance > 333 ohm) 11 = test fail 12:8 amprfln ro 0x00 retain amplitude of reflection the amplitude of reflection is stored in these register bits. these amplitude bits range from 0x07 to 0x1f. 0x1f = maximum positive amplitude 0x13 = zero amplitude 0x07 = maximum negative amplitude these bits are valid after completion of vct (bit 15) and if the vct test status bits (bits 14:13) have not indicated test failure. 7:0 distrfln ro 0x00 retain distance of reflection these bits refer to the approximate distance ( 1m) to the open/short location, measured at nominal conditions (room temperature and typical vdds) these bits are valid after completion of vct (bit 15) and if the vct test status bits (bit 14:13) have not indicated test failure.
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 82 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 52: vct? register for mdip/n[1] pins register 27 bits field mode hw rst sw rst description 15 reserved ro always 0 always 0 reserved 14:13 vcttst ro 0x0 retain vct test status the vct test status bits are valid after completion of vct. 00 = valid test, normal cable (no short or open in cable) 01 = valid test, short in cable (impedance < 33 ohm) 10 = valid test, open in cable (impedance > 333 ohm) 11 = test fail 12:8 amprfln ro 0x00 retain amplitude of reflection the amplitude of reflection is stored in these register bits. these amplitude bits range from 0x07 to 0x1f. 0x1f = maximum positive amplitude 0x13 = zero amplitude 0x07 = maximum negative amplitude these bits are valid after completion of vct (bit 15) and if vct test status bits (bit 14:13) have not indicated test failure. 7:0 distrfln ro 0x00 retain distance of reflection these bits refer to the approximate distance ( 1m) to the open/short location, measured at nominal conditions (room temperature and typical vdds) these bits are valid after completion of vct (bit 15) and if vct test status bits (bits 14:13) have not indicated test failure.
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 83 table 53: phy specific control register ii register 28 bits field mode hw rst sw rst description 15:12 reserved r/w 0x0 retain must be 0000 11:10 mac interface mode r/w see desc. update during hardware reset register 28.11:10 defaults as fol- lows mode[2:0] 28.11:10 000 00 001 01 010 00 011 10 100 10 110 11 111 01 00 = rgmii where receive clock transition when data transitions 01 = rgmii where receive clock transition when data stable 10 = non-source synchronous mii 11 = source synchronous mii 9:5 reserved r/w 0x00 update set to 00000 4 enlinelpbk r/w 0x0 retain 0 = disable line loopback 1 = enable line loopback 3 softwaremedia select r/w see desc. update during hardware reset regist er 28.3 defaults as follows mode[2:0] 28.3 000 0 001 0 010 1 011 0 100 1 110 0 111 1 0 = select copper media 1 = select fiber media 2 tdrwaittime r/w 0x0 retain 0 = wait time is 1.5s before tdr test is started 1 = wait time is 25 ms before tdr test is started 1 enrxclk r/w 0x1 update 0 = disable mac interface clock (rxclk) in sleep mode 1 = enable mac interface clock (rxclk) in sleep mode 0 selclsa r/w 0x0 update 0 = select class b driver (typically used in cat 5 appli- cations) 1 = select class a driver - available for 100base-tx mode only (typically used in backplane or direct connect applications, but may be used with cat 5 applications)
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 84 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 54: test mode select register 29 bits field mode hw rst sw rst description 15:5 reserved r/w 0x000 retain must set to all 0s. 4:0 page r/w 0x00 retain register 30 page table 55: crc status register register 30_9 bits field mode hw rst sw rst description 15:8 crc error count ro 0x00 retain represents the crc error count for received packets since 30_9.0 is set 7:1 reserved r/w always 0 0x00 0000000 0 crc enable r/w 0x0 retain 1=enable crc checker for all ports. 0=disable crc checker for all ports
register description copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 85 table 56: mac interface output impedance calibration override register 30_10 bits field mode hw rst sw rst description 15 restart calibra- tion r/w, sc 0x0 retain calibration will start once bit 15 is set to 1. 0 = normal 1 = restart 14 calibration complete ro 0x0 retain calibration is done once bit 14 becomes 1. 0 = not done 1 = done 13 reserved r/w 0x0 retain 0 12:8 pmos value r/w see descr retain 00000 = all fingers off 11111 = all fingers on the automatic calibrated values are stored here after calibration completes. once latch is set to 1 the new calibration value is writ- ten into the i/o pad. the automatic calibrated value is lost. 7 reserved rw 0x0 retain 0 6latch r/w, sc 0x0 retain 1 = latch in new value. this bit self clears. (used for manual settings) 5pmos/nmos select r/w 0x0 retain 0 = nmos value written when latch is set to 1. 1 = pmos value written when latch is set to 1. 4:0 nmos value r/w see descr retain 00000 = all fingers off 11111 = all fingers on the automatic calibrated values are stored here after calibration completes. once latch is set to 1 the new calibration value is writ- ten into the i/o pad. the automatic calibrated value is lost.
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 86 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 57: mac interface output impedance target register 30_11 bits field mode hw rst sw rst description 15:7 reserved ro 0x000 0x000 000000000 6:4 calibration pmos target impedance rw 0x4 retain 000 = 80 ohm 001 = 69 ohm 010 = 61 ohm 011 = 54 ohm 100 = 49 ohm 101 = 44 ohm 110 = 41 ohm 111 = 38 ohm 3 reserved ro 0x0 0x0 0 2:0 calibration nmos target impedance rw 0x4 retain 000 = 80 ohm 001 = 69 ohm 010 = 61 ohm 011 = 54 ohm 100 = 49 ohm 101 = 44 ohm 110 = 41 ohm 111 = 38 ohm
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 87 electrical specifications absolute maximum ratings section 4. electrical specifications 4.1. absolute maximum ratings stresses above those listed in absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reli- ability. symbol parameter m in typ max units v dda power supply voltage on avdd with respect to vss -0.5 3.6 v v ddac power supply voltage on avddc with respect to vss -0.5 3.6 v v ddar power supply voltage on avddr with respect to vss -0.5 3.6 v v ddax power supply voltage on avddx with respect to vss -0.5 3.6 v v dd power supply voltage on vdd with respect to vss -0.5 3.6 v v ddo power supply voltage on vddo with respect to vss -0.5 3.6 v v ddor power supply voltage on vddor with respect to vss -0.5 3.6 v v pin voltage applied to any digital input pin -0.5 vddo(r) + 0.7, which- ever is less v t storage storage temperature -55 +125 1 1. 125 c is only used as bake temperature for not more than 24 hours. long term storage (e.g weeks or longer) should be kept at 85 c or lower. c
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 88 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 4.2. recommended operating conditions symbol parameter condition min typ max units v dda 1 1. maximum noise allowed on supplies is 50 mv peak-peak. avdd supply for avdd 2.38 2.5 2.62 v v ddac 1 avddc supply for avddc at 2.5v 2.38 2.5 2.62 v for avddc at 3.3v 3.14 3.3 3.46 v v ddar 1 avddr supply for avddr 2.38 2.5 2.62 v v ddax 1 avddx supply for avddx at 3.3v 3.14 3.3 3.46 v v dd 1 dvdd supply for dvdd 1.14 1.2 1.26 v v ddo 1 vddo supply for vddo at 2.5v 2.38 2.5 2.62 v for vddo at 3.3v 3.14 3.3 3.46 v v ddor 1 vddor supply for vddor at 2.5v 2.38 2.5 2.62 v for vddor at 3.3v 3.14 3.3 3.46 v rset internal bias reference resistor connected to v ss 1980 2000 2020 t a ambient operating temperature commercial parts 0 70 2 2. commercial operating temperatures are typically below 70 c, e.g, 45 c ~55 c. the 70 c max is marvell ? specification limit c industrial parts 3 3. industrial part numbers have an "i" following the commercial part numbers. see " ?ordering part numbers and package mark- ings? on page 123 for details. -40 85 c t j maximum junction temperature 125 4 4. refer to white paper on tj thermal calculations for more information. c
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 89 electrical specifications package thermal information 4.3 package thermal information 4.3.1 88e3015 device 56-pin qfn package symbol parameter condition min typ max units ja thermal resistance - junction to ambient of the 56-pin qfn package ja = (t j - t a) / p p = total power dissipa- tion jedec 3 in. x 4.5 in. 4-layer pcb with no air flow 33.40 c/w jedec 3 in. x 4.5 in. 4-layer pcb with 1 meter/sec air flow 29.50 c/w jedec 3 in. x 4.5 in. 4-layer pcb with 2 meter/sec air flow 28.20 c/w jedec 3 in. x 4.5 in. 4-layer pcb with 3 meter/sec air flow 27.50 c/w jt thermal characteristic parameter 1 - junction to top center of the 56-pin qfn package jt = (t j -t c )/p. p = total power dissipa- tion 1. refer to white paper tj thermal calculations for more information. jedec 3 in. x 4.5 in. 4-layer pcb with no air flow 0.55 c/w jedec 3 in. x 4.5 in. 4-layer pcb with 1 meter/sec air flow 0.94 c/w jedec 3 in. x 4.5 in. 4-layer pcb with 2 meter/sec air flow 1.19 c/w jedec 3 in. x 4.5 in. 4-layer pcb with 3 meter/sec air flow 1.33 c/w jc thermal resistance 1 - junction to case for the 56-pin qfn package jc = (t j - t c )/ ptop ptop = power dissipa- tion from the top of the package jedec with no air flow 17.90 c/w jb thermal resistance 1 - junction to board for the 56-pin qfn package jb = (t j - t b )/ p bottom p bottom = power dissipa- tion from the bottom of the package to the pcb surface. jedec with no air flow 21.80 c/w
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 90 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 4.3.2 88E3018 device 64-pin qfn package symbol parameter condition min typ max units ja thermal resistance - junction to ambient of the 64-pin qfn package ja = (t j - t a) / p p = total power dissipa- tion jedec 4 in. x 4.5 in. 4-layer pcb with no air flow 32.40 c/w jedec 4 in. x 4.5 in. 4-layer pcb with 1 meter/sec air flow 28.60 c/w jedec 4 in. x 4.5 in. 4-layer pcb with 2 meter/sec air flow 27.40 c/w jedec 4 in. x 4.5 in. 4-layer pcb with 3 meter/sec air flow 26.70 c/w jt thermal characteristic parameter 1 - junction to top center of the 64-pin qfn package jt = (t j -t c )/p. p = total power dissipa- tion 1. refer to white paper tj thermal calculations for more information. jedec 4 in. x 4.5 in. 4-layer pcb with no air flow 0.52 c/w jedec 4 in. x 4.5 in. 4-layer pcb with 1 meter/sec air flow 0.89 c/w jedec 4 in. x 4.5 in. 4-layer pcb with 2 meter/sec air flow 1.12 c/w jedec 4 in. x 4.5 in. 4-layer pcb with 3 meter/sec air flow 1.26 c/w jc thermal resistance 1 - junction to case for the 64-pin qfn package jc = (t j - t c )/ ptop ptop = power dissipa- tion from the top of the package jedec with no air flow 17.30 c/w jb thermal resistance 1 - junction to board for the 64-pin qfn package jb = (t j - t b )/ p bottom p bottom = power dissipa- tion from the bottom of the package to the pcb surface. jedec with no air flow 21.10 c/w
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 91 electrical specifications current consumption 4.4 current consumption note the following current consumption num bers are shown when external supplies are used. if internal regulators are used, the current consumption will not change; however, the power consumed inside the package will increase. 4.4.1 current consumption avdd + center tap 4.4.2 current consumption avddc (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ 1,2 1. the values listed are ty pical values with three leds and auto-negotiation on. 2. if the 2.5v pnp option is used, then this current is consumed by avddx. max units i dda 2.5v power to analog core, analog i/o avdd 10base-t idle 25 ma 10base-t with traffic 90 ma 100base-tx with traffic or idle 54 ma auto-negotiation with no link 25 ma 100base-fx with traffic or idle 57 ma coma 7 ma sleep (energy detect+?) 25 ma power down 7 ma (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ 1 1. the values listed are typical values with three leds and auto-negotiation on. max units i ddc 2.5v/3.3v power to analog core avddc 10base-t idle 5 ma 10base-t with traffic 5 ma 100base-tx with traffic or idle 5ma auto-negotiation with no link 5ma 100base-fx with traffic or idle 4ma coma 4 ma sleep (energy detect+?) 4 ma power down 4 ma
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 92 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver note the following current consumption numbers are shown when external supplies are used. if internal regulators are used, the current consumption will no t change; however, the power consumed inside the package will increase. 4.4.3 current consumption dvdd 4.4.4 current consumption vddo + vddor (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ 1,2 1. the values listed are typical values with three leds and auto-negotiation on. 2. if the internal 1.2v regulator is us ed, the dvdd current is consumed by avddr. max units i dd 1.2v power to digital i/o dvdd 10base-t idle 7 ma 10base-t with traffic 8 ma 100base-tx with traffic or idle 25 ma auto-negotiation with no link 7ma 100base-fx with traffic or idle 11 ma coma 4 ma sleep (energy detect+?) 8 ma power down 4 ma (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ 1 1. the values listed are typical values with three leds and auto-negotiation on. max units i ddo 2.5v/3.3v non-mac interface digital i/o and mac interface digi- tal i/o vddo 10base-t idle 1 ma 10base-t with traffic 5 ma 100base-tx with traffic or idle 8ma auto-negotiation with no link 1 ma 100base-fx with traffic or idle 9ma coma 3 ma sleep (energy detect+?) 1 ma power down 2 ma
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 93 electrical specifications dc operating conditions 4.5. dc operating conditions table 58: 88E3018 device internal resistor description 4.5.1 non-mac interface digital pins (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter pins condition min typ max units vih input high voltage all digital inputs vddo = 3.3v 2.31 v vddo = 2.5v 1.75 v vil input low voltage all digital inputs vddo = 3.3v 0.99 v vddo = 2.5v 0.75 v voh high level output voltage all digital outputs ioh = -4 ma vddo - 0.4v v vol low level output voltage all digital outputs iol = 4 ma 0.4 v i ilk input leakage current with internal pull-up resistor 10 -50 ua all others without resistor 10 ua cin input capacitance all pins 5 pf 88e3015 device pin # 88E3018 device pin # pin name resistor -- 13 tck internal pull-up -- 14 tms internal pull-up -- 37 trstn internal pull-up -- 12 tdi internal pull-up 22 4 coman internal pull-up
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 94 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 4.5.2 stub-series transceiver logic (sstl_2) figure 16: sstl_2 termination circuit note this circuit can be used if termination is required. this circuit can also be used unterminated if the interconnect is short. figure 17: sstl_2 input voltage levels z = 50 50 ohm vddo/2 vddo = 2.5v i oh = -8 ma i ol = 8 ma v ref = vddo /2 vddq vss vil(ac) vil(dc) vref vih(dc) vih(ac)
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 95 electrical specifications dc operating conditions table 59: reference i/o parameters 1 1. these numbers are preliminary. marvell? re serves the right to change these parameters. parameter description corner 2.5v sstl_2 3.3v sstl_2 units vddq output supply voltage min 2.38 3.14 v nom 2.5 3.3 v max 2.62 3.46 v vref input reference voltage min 1.19 1.57 v nom 1.25 1.65 v max 1.31 1.73 v vtt termination voltage min vref - 0.04 v nom vref v max vref + 0.04 v vih(dc) dc input logic high min vref + 0.18 vref + 0.25 v max vddq + 0.30 vddq + 0.30 v vil(dc) dc input logic low min - 0.30 - 0.30 v max vref - 0.18 vref - 0.25 v vih(ac) ac input logic high min vref + 0.35 vref + 0.50 v max----v vil(ac) ac input logic low min -- -- v max vref - 0.35 vref - 0.50 v voh(dc) dc output logic high min v max v vol(dc) dc output logic low min v max v voh(ac) ac output logic high min vtt + 0.57 vtt + 0.9 v max -- v vol(ac) ac output logic low min -- v max vtt - 0.57 vtt - 0.9 v ioh(dc) output minimum source dc cur- rent min 7.60 7.60 ma max----ma iol(dc) output minimum sink dc current min 7.60 7.60 ma max----ma input timing reference level vref vref v input signal swing 1.5 2.0 v input signal edge rate 1.0 1.0 v/ns output timing reference level vddq/2 vddq/2 v
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 96 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 4.5.3 ieee dc transceiver parameters ieee tests are typically based on template and cannot simply be specified by a number. for an exact description of the template and the test conditions, refer to the ieee specifications. ? 10base-t ieee 802.3 clause 14 ? 100base-tx ansi x3.263-1995 (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ max units v odiff absolute peak differ- ential output voltage mdip/n[0] mdip/n[1] 10base-t no cable 2.2 2.5 2.8 v mdip/n[0] mdip/n[1] 10base-t cable model 585 1 1. ieee 802.3 clause 14-2000, figure 14.9 shows the template for th e ?far end? wave form. this template allows as little as 49 5 mv peak differential voltage at the far end receiver. mv mdip/n[0] mdip/n[1] 100base-fx mode 0.4 0.8 1.2 v mdip/n[0] mdip/n[1] 100base-tx mode 0.950 1.0 1.05 v overshoot mdip/n[0] mdip/n[1] 100base-tx mode 0 5% v amplitude symmetry (p/n) mdip/n[0] mdip/n[1] 100base-tx mode 0.98x 1.02x v+/v- v idiff peak differential input volt- age accept level mdip/n[0] mdip/n[1] 10base-t mode 585 2 2. the input test is actually a template test, ieee 802.3 claus e 14-2000. figure 14.17 shows the template for the receive wave form. mv mdip/n[0] mdip/n[1] 100base-fx mode 200 mv peak differ- ential input voltage reject level mdip/n[0] mdip/n[1] 100base-fx mode 100 mv signal detect assertion mdip/n[0] mdip/n[1] 100base-tx mode 1000 460 3 3. the ansi tp-pmd specification requires that any received si gnal with peak-to-peak differential amplitude greater than 1000 m v should turn on signal detect (internal signal in 100base-tx mode ). the will accept signals typi cally with 460 mv peak-to-peak differential amplitude. mv peak- peak signal detect de-assertion mdip/n[0] mdip/n[1] 100base-tx mode 200 360 4 4. the ansi tp-pmd specification require s that any received signal with peak-to-peak differential amplitude less than 200 mv should be de-assert signal detect (internal signal in 100base-tx mode). the will reject signals typically with peak-to-peak di f- ferential amplitude less than 360 mv. mv peak- peak
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 97 electrical specifications ac electrical specifications 4.6 ac electrical specifications 4.6.1 reset and configuration timing figure 18: reset timing (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter condition min typ max units t pu_ reset power up to hardware de-asserted 10 ms t su_clk number of valid refclk cycles prior to resetn de-asserted 10 clks power clk resetn t pu_reset t su_clk
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 98 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver figure 19: clock timing 4.6.2 xtal_in input clock timing 1 (over full range of values listed in the recommended operating conditions unless otherwise specified) 1. if the crystal option is used, ensure that the frequency is 25 mhz 50 ppm. capacitors must be chosen carefully - see appli cation note supplied by the crystal vendor. symbol parameter condition min typ max units t p_xtal_in xtal_in period 25 mhz 40 -50 ppm 40 40 +50 ppm ns t h_xtal_in xtal_in high time 25 mhz 14 20 26 ns t l_xtal_in xtal_in low time 25 mhz 14 20 26 ns t r_xtal_in xtal_in rise v il (max) to v ih (min) - 25 mhz -3.0-ns t f_xtal_in xtal_in fall v ih (min) to v il (max) - 25 mhz -3.0-ns t j_xtal_in xtal_in total jitter 2 2. pll generated clocks are not recommended as input to xtal_in si nce they can have excessive jitter. zero delay buffers are al so not recommended for the same reason. 25 mhz - - 200 ps 3 3. broadband peak-peak = 200 ps, broadband rms = 3 ps, 12 khz to 20 mhz rms = 1 ps. t p_xtal_in t h_xtal_in t l_xtal_in t r_xtal_in v ih v il t f_xtal_in xtal_in input
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 99 electrical specifications mii interface timing 4.7 mii interface timing 4.7.1 100 mbps mii transmit timing - non source synchronous (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_mii_ tx_clk mii setup time 15 ns t hd_mii_ tx_clk mii hold time 0 ns t h_mii_ tx_clk tx_clk high 18 20 22 ns t l_mii_ tx_clk tx_clk low 18 20 22 ns t p_mii_ tx_clk tx_clk period 40 ns 4.7.2 10 mbps mii transmit timing - non source synchronous (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_mii_ tx_clk mii setup time 15 ns t hd_mii_ tx_clk mii hold time 0 ns t h_mii_ tx_clk tx_clk high 190 200 210 ns t l_mii_ tx_clk tx_clk low 190 200 210 ns t p_mii_ tx_clk tx_clk period 400 ns
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 100 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver figure 20: mii transmit timing 4.7.3 100 mbps mii transmit timing - source synchronous (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_mii_ tx_clk mii setup time 2.75 ns t hd_mii_ tx_clk mii hold time 1.50 ns t h_mii_ tx_clk tx_clk high 10 20 30 ns t l_mii_ tx_clk tx_clk low 10 20 30 ns t p_mii_ tx_clk tx_clk period 40 ns 4.7.4 10 mbps mii transmit ti ming - source synchronous (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_mii_ tx_clk mii setup time 2.75 ns t hd_mii_ tx_clk mii hold time 1.50 ns t h_mii_ tx_clk tx_clk high 100 200 300 ns t l_mii_ tx_clk tx_clk low 100 200 300 ns t p_mii_ tx_clk tx_clk period 400 ns tx_clk t h_mii_tx_clk t l_mii_tx_clk t p_mii_tx_clk v ih_mii (min.) v il_mii (max.) v ih_mii (min.) v il_mii (max.) txd[7:0] tx_ctrl tx_er t su_mii_tx_clk t hd_mii_tx_clk
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance docum ent classification: proprietary information page 101 electrical specifications mii interface timing figure 21: mii receive timing 4.7.5 100 mbps mii receive timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_mii_ rx_clk mii output to clock 16 ns t hd_mii_ rx_clk mii clock to output 16 ns t h_mii_ rx_clk rx_clk high 18 20 22 ns t l_mii_ rx_clk rx_clk low 18 20 22 ns t p_mii_ rx_clk rx_clk period 40 ns 4.7.6 10 mbps mii receive timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_mii_ rx_clk mii output to clock 190 ns t hd_mii_ rx_clk mii clock to output 190 ns t h_mii_ rx_clk rx_clk high 190 200 210 ns t l_mii_ rx_clk rx_clk low 190 200 210 ns t p_mii_ rx_clk rx_clk period 400 ns rx_clk t h_mii_rx_clk t l_mii_rx_clk t p_mii_rx_clk v oh_mii (min.) v ol_mii (max.) v oh_mii (min.) v ol_mii (max.) rxd[7:0] rx_ctrl rx_er t su_mii_rx_clk t hd_mii_rx_clk
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 102 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 4.8 rgmii interface timing 4.8.1 rgmii transmit timing figure 22: rgmii transmit timing 4.8.1.1 100 mbps rgmii transmit timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_rgmii_ tx_clk rgmii setup time 1.0 ns t hd_rgmii_ tx_clk rgmii hold time 0.8 ns t h_rgmii_ tx_clk tx_clk high 10 20 30 ns t l_rgmii_ tx_clk tx_clk low 10 20 30 ns t p_rgmii_ tx_clk tx_clk period 40 ns 4.8.1.2 10 mbps rgmii transmit timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_rgmii_ tx_clk rgmii setup time 1.0 ns t hd_rgmii_ tx_clk rgmii hold time 0.8 ns t h_rgmii_ tx_clk tx_clk high 100 200 300 ns t l_rgmii_ tx_clk tx_clk low 100 200 300 ns t p_rgmii_ tx_clk tx_clk period 400 ns tx_clk txd[3:0], tx_ctl t su_rgmii_tx_clk t hd_rgmii_tx_clk t su_rgmii_tx_clk t hd_rgmii_tx_clk t l_rgmii_tx_clk t h_rgmii_tx_clk t p_rgmii_tx_clk
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance docum ent classification: proprietary information page 103 electrical specifications rgmii interface timing 4.8.2 rgmii receive timing 4.8.2.1 register 28.11:10 = 00 figure 23: rgmii rx_clk delay timing - register 28.11:10 = 00 4.8.2.2 register 28.11:10 = 01 (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter min typ max units t skew all speeds - 0.5 0.5 ns 100 mbps rgmii receive timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_rgmii_ rx_clk rgmii output to clock 5 ns t hd_rgmii_ rx_clk rgmii clock to output 5 ns t h_rgmii_ rx_clk rx_clk high 18 20 22 ns t l_rgmii_ rx_clk rx_clk low 18 20 22 ns t p_rgmii_ rx_clk rx_clk period 40 ns rx_clk rxd[3:0], rx_ctrl t skew t skew t skew t skew
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 104 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver figure 24: rgmii rx_clk delay timing - re gister 28.11:10 = 01 (add delay) 10 mbps rgmii receive timing (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter condition min typ max units t su_rgmii_ rx_clk rgmii output to clock 80 ns t hd_rgmii_ rx_clk rgmii clock to output 80 ns t h_rgmii_ rx_clk rx_clk high 190 200 210 ns t l_rgmii_ rx_clk rx_clk low 190 200 210 ns t p_rgmii_ rx_clk rx_clk period 400 ns rx_clk rxd[3:0], rx_ctl t su_rgmii_rx_clk t hd_rgmii_rx_clk t su_rgmii_rx_clk t hd_rgmii_rx_clk t l_rgmii_rx_clk t h_rgmii_rx_clk t p_rgmii_rx_clk
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance docum ent classification: proprietary information page 105 electrical specifications latency timing 4.9 latency timing 4.9.1 mii to 100base-tx transmit latency timing (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter condition min typ max units t as_txctrl_ col_100 100base-tx tx_ctrl asserted to col asserted 184 202 ns t as_txctrl_ mdi_100 100base-tx tx_ctrl asserted to /j/ 208 234 ns t da_txctrl_ col_100 100base-tx tx_ctrl de-asserted to col de-asserted 192 210 ns t da_txctrl_ mdi_100 100base-tx tx_ctrl de-asserted to /t/ 208 234 ns 4.9.2 mii to 10base-t transmit latency timing (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter condition min typ max units t as_txctrl_ col_10 10base-t tx_ctrl asserted to col asserted 1700 1810 ns t as_txctrl_ mdi_10 10base-t tx_ctrl asserted to preamble 1845 1960 ns t da_txctrl_ col_10 10base-t tx_ctrl de-asserted to col de-asserted 1800 1910 ns t da_txctrl_ mdi_10 10base-t tx_ctrl de-asserted to etd 1845 1960 ns
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 106 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver figure 25: mii to 10/100 transmit latency timing note the collision (col) diagram assumes that the device was already receiving data when transmission started. in half-duplex mode this will ca use a collision. compare this figure with figure 26 . preamble /k/ /j/ /t/ /r/ etd col tx_clk t da_txctrl_mdi t da_txctrl_col t as_txctrl_col t as_txctrl_mdi tx_ctrl 100 10
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance docum ent classification: proprietary information page 107 electrical specifications latency timing 4.9.3 100base-tx to m ii receive latency timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t as_mdi_ crs_100 100base-tx mdi start of packet to crs asserted 128 144 ns t as_mdi_ col_100 100base-tx mdi start of packet to col asserted 128 144 ns t as_mdi_ rxctrl_100 100base-tx mdi start of packet to rx_ctrl asserted 239 297 ns t da_mdi_ crs_100 100base-tx mdi /t/ to crs de-asserted 200 240 ns t da_mdi_ col_100 100base-tx mdi /t/ to col de-asserted 200 240 ns t da_mdi_ rxctrl_100 100base-tx mdi /t/ to rx_ctrl de-asserted 239 297 ns 4.9.4 10base-t to mii receive latency timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t as_mdi_ crs_10 10base-t mdi start of packet to crs asserted 300 510 ns t as_mdi_ col_10 10base-t mdi start of packet to col asserted 300 510 ns t as_mdi_ rxctrl_10 10base-t mdi start of packet to rx_ctrl asserted 1400 2010 ns t da_mdi_ crs_10 10base-t mdi etd to crs de-asserted 1100 1610 ns t da_mdi_ col_10 10base-t mdi etd to col de-asserted 1100 1610 ns t da_mdi_ rxctrl_10 10base-t mdi etd to rx_ctrl de-asserted 1400 1910 ns
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 108 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver figure 26: 10/100 to mii receive latency timing note this diagram assumes that the device was already tr ansmitting data when data has started to be received from the link partner. in half-duplex mode this will cause a collision. compare this figure with figure 25 . preamble /k/ /j/ /t/ /r/ etd t as_mdi_crs t as_mdi_col t as_mdi_rxctrl t da_mdi_crs t da_mdi_col t da_mdi_rxctrl crs col rx_ctrl 100 10
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance docum ent classification: proprietary information page 109 electrical specifications latency timing figure 27: rgmii/mii to 10/1 00 transmit latency timing 4.9.5 rgmii to 100base-tx transmit latency timing (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter condition min typ max units t as_txc_ mdi_100 100base-tx tx_ctrl asserted to /j/ 248 274 ns t da_txc_ mdi_100 100base-tx tx_ctrl de-asserted to /t/ 248 274 ns 4.9.6 rgmii to 10base-t transmit latency timing (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter condition min typ max units t as_txc_ mdi_10 10base-t tx_ctrl asserted to preamble 2245 2360 ns t da_txc_ mdi_10 10base-t tx_ctrl de-asserted to etd 2245 2360 ns preamble /k/ /j/ /t/ /r/ etd tx_clk t da_txc_mdi t as_txc_mdi tx_ctrl 100 10
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 110 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 4.9.7 100base-tx to rgm ii receive latency timing 4.9.8 10base-t to rgmi i receive latency timing figure 28: 10/100 to rgmii receive latency timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t as_mdi_ rxc_100 100base-tx mdi start of packet to rx_ctrl asserted 231 297 ns t da_mdi_ rxc_100 100base-tx mdi /t/ to rx_ctrl de-asserted 231 297 ns (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t as_mdi_ rxc_10 10base-t mdi start of packet to rx_ctrl asserted 1300 1910 ns t da_mdi_ rxc_10 10base-t mdi etd to rx_ctrl de-asserted 1300 1910 ns preamble /k/ /j/ /t/ /r/ etd t as_mdi_rxc t da_mdi_rxc rx_ctrl 100 10 rx_clk
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 111 electrical specifications serial management timing 4.10 serial management timing figure 29: mii serial management timing (over full range of values listed in the recommend ed operating conditions unless otherwise specified) symbol parameter condition min typ max units t dly_mdio mdc to mdio (output) delay time 025ns t su_ mdio mdio (input) to mdc setup time 10 ns t hd_ mdio mdio (input) to mdc hold time 10 ns t p_ mdc mdc period 120 ns t h_ mdc mdc high 30 ns t l_ mdc mdc low 30 ns valid data mdc t hd_mdio t su_mdio mdc t p_mdc t dly_mdio mdio (output) mdio (input) t h_mdc t l_mdc
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 112 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 4.11 jtag timing figure 30: jtag timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t p_tck tck period 40 ns t h_tck tck high 12 ns t l_tck tck low 12 ns t su_tdi tdi, tms to tck setup time 10 ns t hd_tdi tdi, tms to tck hold time 10 ns t dly_tdo tck to tdo delay 0 20 ns tck tdo t dly_tdo t su_tdi t hd_tdi t h_tck t l_tck tms tdi t p_tck
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 113 package mechanical dimensions 88e3015 package mechanical dimensions section 5. package mechanical dimensions 5.1 88e3015 package mechanical dimensions figure 31: 88e3015 56-pin qfn package (all dimensions in mm.) detail : a 0.6max "a" e 0.08 e2 c a d2 0.6max seating plane b "b" e e1 1.0mm ? 1 3 2 n d1 d a2 a detail : b l b x 4 o a1 a3
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 114 document classification: proprietary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 60: dimensions of the 56-pin qfn package table 61: 56-pin qfn mechanical dimensions dimensions in mm symbol min nom max a 0.80 0.85 1.00 a1 0.00 0.02 0.05 a2 -- 0.65 1.00 a3 0.20 ref b 0.18 0.23 0.30 d 8.00 bsc d1 7.75 bsc e 8.00 bsc e1 7.75 bsc e 0.50 bsc l 0.30 0.40 0.50 0 -- 12 aaa -- -- 0.15 bbb -- -- 0.10 chamfer -- -- 0.60 die pad size symbol dimension in mm d 2 4.37 0.20 e 2 4.37 0.20
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 115 package mechanical dimensions 88E3018 package mechanical dimensions 5.2 88E3018 package mechanical dimensions figure 32: 88E3018 64-pin qfn package (all dimensions in mm.) detail : b 0.6max e e2 0.08 c a seating plane "a" d2 c ''b'' aaa e e1 n 3 2 1 d d1 l a a2 b detail : a 0.6max b a1 a3 x 4 o 1.0mm
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 116 document classification: proprietary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver table 62: 64-pin qfn mechanical dimensions dimensions in mm symbol min nom max a 0.80 0.85 1.00 a1 0.00 0.02 0.05 a2 -- 0.65 1.00 a3 0.20 ref b 0.18 0.23 0.30 d 9.00 bsc d1 8.75 bsc e 9.00 bsc e1 8.75 bsc e 0.50 bsc l 0.30 0.40 0.50 0 -- 12 aaa -- -- 0.25 bbb -- -- 0.10 chamfer -- -- 0.60 die pad size symbol dimension in mm d 2 3.78 0.20 e 2 3.78 0.20
application examples 10base-t/100base-tx circuit application copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 117 section 6. application examples 6.1 10base-t/100base-tx circuit application figure 33: 10base-t/100base-tx circuit application 88e3015/ 88E3018 rj-45 mdip[0] mdin[0] transformer 2k 1% rset mdip[1] mdin[1] rx p_p rxn_p tx p_p tx n_p tx p_s tx n_s cmt rx p_s rx n_s txp (1) txn (2) rxp (3) unused (4) unused (5) rxn (6) 1000pf 3 kv unused (7) unused (8) 49.9 49.9 0.01 f 49.9 2.5v rct_pt 75 75 49.9 49.9 49.9 0.1 f 0.01 f tct_pt 2.5v 0.1 f 49.9
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 118 document classification: proprietary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 6.2 fx interface to 3.3v fiber transceiver figure 34: fx interface to 3.3v fiber transceiver mdip[0] mdip[1] tdp tdn rdp rdn sd 88e3015/ 88E3018 terminate at fiber inputs 3.3v tbd 3.3v 130 130 terminate at 88e3015/88E3018 inputs 82 82 terminate at 88e3015/ 88E3018 inputs tbd tbd tbd tbd tbd tbd tbd 69 69 174 174 0.01 uf 0.01 uf 0.01 uf 0.01 uf 3.3v 3.3v sigdet mdin[0] mdin[1] tbd -- to be determined by the application of the fiber module.
application examples transmitter - receiver diagram copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 119 6.3 transmitter - receiver diagram figure 35: transmitter - receiver diagram off 69 174 174 174 + 69 x 3.3 = 2.36v sink 0 ma on 69 174 sink 15 ma v = 3.3 - (15 + i) 69 = 174i v v = v = 1.62v i 3.3v 3.3v 2.36 + 1.62 2 common mode: marvell ? 100base-fx phy transmitter 1k 1k
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 120 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 6.4 88E3018 to 88e3015 backplane connection - 100base-fx interface figure 36: 88E3018 to 88e3015 backplane connection - 100base-fx interface mdip[0] mdip[1] 88e3015 1 k 1 k 174 174 2.5v or 3.3v 1 k 1 k
application examples 88E3018 to another vendor?s phy - 100base-fx interface through a backplane copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 121 6.5 88E3018 to another vendor?s phy - 100base-fx inter- face through a backplane figure 37: 88E3018 to another vendor?s phy - 100base-fx interface through a backplane mdip[0] mdip[1] 88E3018 3.3v tbd 3.3v 1 k 1 k 1 k 1 k tbd tbd tbd tbd tbd tbd tbd 69 69 174 174 0.01 uf 0.01 uf 0.01 uf 0.01 uf 3.3v 3.3v sd mdin[0] mdin[1] txn txp rxp rxn other phy with 100mb-fx 2.5v or 3.3v sigdet terminate at 88E3018 inputs tbd tbd : termination requirements are to be determined by the application of the vendors specification note: assume source termination required
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 122 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver 6.6 marvell ? phy to marvell phy direct connection figure 38: marvell ? phy to marvell phy direct connection mdip[0] mdip[1] 88e3015/ 88E3018 174 174 sigdet mdin[0] mdin[1] 88e3015/ 88E3018 sigdet 174 174 69 69 2.5v or 3.3v 2.5v or 3.3v mdip[1] mdin[1] mdip[0] mdin[0]
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 123 order information ordering part numbers and package markings section 7. order information 7.1 ordering part numbers and package markings figure 39 shows the ordering part numbering scheme fo r the 88e3015/88E3018 device. contact marvell ? faes or sales representatives for complete ordering information. figure 39: sample part number table 63: 88e3015/88E3018 part order options - rohs 5/6 compliant package package type part order number 88e3015 56-pin qfn - commercial 88e3015-xx-nnp-c000 88E3018 64-pin qfn - commercial 88E3018-xx-nnc-c000 table 64: 88e3015/88E3018 part order options - rohs 6/6 compliant package package type part order number 88e3015 56-pin qfn - commercial 88e3015-xx-nnp1c000 88E3018 64-pin qfn - commercial 88E3018-xx-nnc1c000 88E3018 64-pin qfn - industrial 88E3018-xx-nnc1i000 ? xx ? xxx ? c000 - t123 part number 88e3015 88E3018 package code nnp = 56-pin qfn nnc = 64-pin qfn environmental "-" = rohs 5/6 package 1 = rohs 6/6 package temperature range c = commercial i = industrial custom code custom code (optional) 88e301x custom code
doc. no. mv-s103657-00, rev. c confidential copyright ? 2006 marvell page 124 document classification: proprie tary information october 26, 2006, advance 88e3015/88E3018 integrated 10/100 fast ethernet transceiver figure 40 is an example of the package marking and pin 1 location for the 88e3015 56-pin qfn commercial rohs 5/6 compliant package. figure 40: 88e3015 56-pin qfn commercial rohs 5/6 compliant package marking and pin 1 location figure 41 is an example of the package marking and pin 1 location for the 88E3018 64-pin qfn commercial rohs 6/6 compliant package. figure 41: 88E3018 64-pin qfn commercial rohs 6/6 compliant package marking and pin 1 location 88e3015-nnp lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) n ote : the above example is not drawn to scale. location of markings is approximate. logo part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6 date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code pin 1 location 88E3018-nnc1 lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) n ote : the above example is not drawn to scale. location of markings is approximate. logo date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code pin 1 location part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6
copyright ? 2006 marvell confidential doc. no. mv-s103657-00, rev. c october 26, 2006, advance document classifi cation: proprietary information page 125 order information ordering part numbers and package markings figure 42 is an example of the package marking and pin 1 location for the 88E3018 64-pin qfn industrial rohs 6/6 compliant package. figure 42: 88E3018 64-pin qfn industrial ro hs 6/6 compliant package marking and pin 1 location 88E3018-nnc1 lot number yyww xx@ country country of origin (contained in the mold id or marked as the last line on the package.) n ote : the above example is not drawn to scale. location of markings is approximate. i logo date code, custom code, assembly plant code yyww = date code xx = custom code @ = assembly location code industrial grade package marking pin 1 location part number, package code, environmental code environmental code - no code = rohs 5/6 1 = rohs 6/6
worldwide corporate offices marvell semiconductor, inc. 5488 marvell lane santa clara, ca 95054, usa tel: 1.408.222.2500 marvell asia pte, ltd. 151 lorong chuan, #02-05 new tech park, singapore 556741 tel: 65.6756.1600 fax: 65.6756.7600 marvell japan k.k. shinjuku center bldg. 44f 1-25-1, nishi-shinjuku, shinjuku-ku tokyo 163-0644, japan tel: 81.(0).3.5324.0355 fax: 81.(0).3.5324.0354 marvell semiconductor israel, ltd. 6 hamada street mordot hacarmel industrial park yokneam 20692, israel tel: 972.(0).4.909.1500 fax: 972.(0).4.909.1501 marvell semiconductor korea, ltd. rm. 603, trade center 159-2 samsung-dong, kangnam-ku seoul 135-731, korea tel: 82.(0).2.551-6070/6079 fax: 82.(0).2.551.6080 radlan computer communications, ltd. atidim technological park, bldg. #4 tel aviv 61131, israel tel: 972.(0).3.645.8555 fax: 972.(0).3.645.8544 worldwide sales offices western us marvell 5488 marvell lane santa clara, ca 95054, usa tel: 1.408.222.2500 fax: 1.408.752.9028 sales fax: 1.408.752.9029 central us marvell 9600 north mopac drive, suite #215 austin, tx 78759, usa tel: 1.512.343.0593 fax: 1.512.340.9970 eastern us/canada marvell parlee office park 1 meeting house road, suite 1 chelmsford, ma 01824 , usa tel: 1.978.250.0588 fax: 1.978.250.0589 europe marvell 5 marchmont gate boundary way hemel hempstead hertfordshire, hp2 7bf united kingdom tel: 44.(0).1442.211668 fax: 44.(0).1442.211543 israel marvell 6 hamada street mordot hacarmel industrial park yokneam 20692, israel tel: 972.(0).4.909.1500 fax: 972.(0).4.909.1501 china marvell 5j1, 1800 zhongshan west road shanghai, prc 200233 tel: 86.21.6440.1350 fax: 86.21.6440.0799 marvell rm. 1102/1103, jintian fudi mansion #9 an ning zhuang west rd. qing he, haidian district beijing, prc 100085 tel: 86.10.8274.3831 fax: 86.10.8274.3830 japan marvell shinjuku center bldg. 44f 1-25-1, nishi-shinjuku, shinjuku-ku tokyo 163-0644, japan tel: 81.(0).3.5324.0355 fax: 81.(0).3.5324.0354 taiwan marvell 2fl., no.1, alley 20, lane 407, sec. 2 ti-ding blvd., nei hu district taipei, taiwan, 114, r.o.c tel: 886.(0).2.8177.7071 fax: 886.(0).2.8752.5707 korea marvell rm. 603, trade center 159-2 samsung-dong, kangnam-ku seoul 135-731, korea tel: 82.(0).2.551-6070/6079 fax: 82.(0).2.551.6080 marvell semiconductor, inc. 5488 marvell lane santa clara, ca 95054, usa tel: 1.408.222.2500 fax: 1.408.752.9028 www.marvell.com for more information, visit our website at: www.marvell.com

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